Electrically erasable programmable read-only memory (EEPROM)...

Details Electrically erasable programmable read-only memory (EEPROM)... Electrically erasable programmable read-only memory (EEPROM)...

2005-10-03

2008-10-07

Chaudhari, Chandra (Department: 2891)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257SE21690

Reexamination Certificate

active

07432159

ABSTRACT:
An EEPROM device includes a device isolation layer disposed at a predetermined region of a semiconductor substrate to define active regions, a pair of control gates crossing the device isolation layers and an active region, a pair of selection gates interposed between the control gates to cross the device isolation layers and the active region and a floating gate and an intergate dielectric pattern stacked sequentially between the control gates and the active region The EEPROM device further includes a gate insulation layer of a memory transistor interposed between the floating gate and the active region and a tunnel insulation layer thinner than the gate insulation layer of the memory transistor and a gate insulation layer of a selection transistor interposed between the selection gates and the active region. The tunnel insulation layer is aligned at one side adjacent to the floating gate.

REFERENCES:
patent: 5455792 (1995-10-01), Yi
patent: 6642103 (2003-11-01), Wils et al.
patent: 6680225 (2004-01-01), Miyagi
patent: 2002/0110985 (2002-08-01), Tseng
patent: 10-2000-0038867 (2000-07-01), None
patent: 10-2002-0002718 (2002-01-01), None

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