Electrically erasable programmable read-only memory device...

Details Electrically erasable programmable read-only memory device... Electrically erasable programmable read-only memory device...

2000-03-14

2001-03-06

Phan, Trong Q. (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S264000

Reexamination Certificate

active

06197636

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to electrically erasable programmable read-only memory devices (EEPROMs), and more particularly, to an EEPROM device in which an active region can be scaled down in size, while mitigating misalignment with respect to a tunnel region, so as to enable high integration of the EEPROM device, and a method for fabricating the same.
2. Description of the Prior Art
Generally, an EEPROM is a nonvolatile memory device where data can be erased and/or programmed in response to electrical signals. An EEPROM comprises a plurality of memory cells, each of which is individually erasable or programmable. Each of the memory cells generally comprises two transistors. For example, an EEPROM memory cell of the floating gate tunnel oxide (FLOTOX) type includes a sense transistor and a selection transistor. The selection transistor selects the associated memory cell for an erasing or programming operation, and the sense transistor actually performs the erasing or programming operation of the associated memory cell. For the programming or erasing operation of each cell, a phenomenon typically referred to as electron tunneling is employed to store a positive or negative charge on a floating gate electrode of the sense transistor. The programming operation is performed by applying a positive voltage to a drain of the sense transistor while a control gate of the sense transistor remains grounded. As a result, electrons tunnel from the floating gate of the sense transistor to the drain thereof via a tunnel dielectric film, thereby causing the floating gate to be positively charged. Each EEPROM memory cell is erased by storing a negative charge on the floating gate of the sense transistor. Such storage of the negative charge is typically achieved by applying a positive voltage to the control gate of the sense transistor while grounding the drain and source of the sense transistor. This biasing causes electrons to tunnel from the drain of the sense transistor to the floating gate thereof via the tunnel dielectric film, resulting in the production of the negative charge on the floating gate.
In order to increase memory capacity in the FLOTOX-type EEPROM, there has recently been proposed a method for reducing the memory cell size of the EEPROM while increasing the integration degree thereof. However, such a method is limited in its fabrication process in that it is difficult to scale a reduced-size tunnel region to be aligned with, and overlapped above, the reduced-size active region. In order to overcome this limitation, contemporary EEPROMs are designed by scaling down the active region with no further scaling down of the tunnel region.
FIG. 1
depicts a layout of a conventional EEPROM cell, which is denoted by the reference numeral
10
. As shown in this drawing, the EEPROM cell
10
comprises an active region
12
and a field isolation region
14
, external to the active region
12
. A drain region
16
and source region
18
of the EEPROM cell
10
are formed in the active region
12
. A source/drain region
17
is formed in a portion of the active region
12
between a selection gate
36
of a selection transistor and a floating gate
22
of a sense transistor. The source/drain region
17
operates in common as both a source of the cell selection transistor and a drain of the cell sense transistor. The EEPROM cell
10
further comprises a tunnel ion implanted region
20
, which overlaps the active region
12
and field isolation region
14
.
In the above-mentioned conventional EEPROM cell
10
, a tunnel region
32
can be obtained by patterning a tunnel opening for the tunnel region
32
on a gate dielectric film to expose a portion of the active region
12
on the substrate and then growing or depositing a tunnel dielectric film on the exposed active region portion to a thickness of 50-100 Å. The active region
12
has the same width throughout the entire area overlapped by the floating gate
22
. Also, the active region
12
is wide enough to prevent any misalignment with the tunnel region
32
.
However, in the case where the active region
12
is reduced, or scaled down, in size, the margin of overlap G
1
of the active region
12
with respect to the tunnel region
32
is reduced, thus increasing the likelihood of misalignment between the active region
12
and tunnel region
32
. As a result, the tunnel region
32
is likely to overlap both the active region
12
and field isolation region
14
, or the tunnel dielectric film in the tunnel region
32
may be formed to overlap both the active region
12
and field isolation region
14
, thereby raising the possibility that the tunnel dielectric film will be degraded in quality. As a consequence, faulty conditions may arise, where the EEPROM cell is inconsistently or inaccurately programmed, the cell threshold voltage Vth is not constant in level, and device lifetime may be adversely affected.
SUMMARY OF THE INVENTION
In view of the above limitations, it is an object of the present invention to provide an EEPROM device and method for fabricating the same in which an active region can be scaled down in size while mitigating and/or eliminating misalignment with respect to a tunnel region, resulting in a reduction in cell size.
In accordance with one aspect of the present invention, the above and other objects are accomplished by an electrically erasable programmable read-only memory device comprising a substrate having an active region, a field isolation region for isolating the active region, and extension areas integrally extended from and interconnected with portions of the active region in the neighborhood of a tunnel region to enlarge an overlap margin between the active region and tunnel region; a tunnel ion implanted region formed in a portion of the active region including the tunnel region; a tunnel dielectric film formed on a portion of the active region corresponding to the tunnel region; a gate dielectric film formed on the remaining portion of the active region except for the portion corresponding to the tunnel region; a floating gate formed in common on the tunnel region a nd active region; a control gate formed on the floating gate via an insulating film; a selection gate formed on the gate dielectric film at a predetermined distance from the control gate; and a source region, a drain region and a source/drain region being self-aligned with the selection gate and floating gate and formed on the active region.
Preferably, each of the extension areas is of a width that extends to ½ the distance between an edge of said active region and an edge of said floating gate, and of a length that extends on a first end to a middle location between said selection gate and control gate, and on a second end to the source region.
In accordance with another aspect of the present invention, there is provided a method for fabricating an electrically erasable programmable read-only memory device, comprising the steps of forming a field isolation region on an area of a substrate except for an active region to isolate the active region on the substrate and then forming extension areas integrally extended from and interconnected with portions of the active region in the neighborhood of a tunnel region to enlarge an overlap margin between the active region and tunnel region; implanting impurity ions into a portion of the active region including the tunnel region to form a tunnel ion implanted region therein; forming a gate dielectric film on the active region; etching a portion of the gate dielectric film corresponding to the tunnel region to expose an underlying active region portion; forming a tunnel dielectric film on the exposed active region portion; forming a floating gate and an overlying insulating film in common on the tunnel dielectric film and gate dielectric film; and forming a control gate on the floating gate via the insulating film and then forming a selection gate on the gate dielectric film at a predetermined distance from the floating g

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