EEPROM memory cell and method of forming the same

Details EEPROM memory cell and method of forming the same EEPROM memory cell and method of forming the same

2005-07-12

2005-07-12

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257S316000, C257S318000, C257S321000, C365S185280, C365S149000, C438S258000, C438S281000

Reexamination Certificate

active

06916711

ABSTRACT:
An EEPROM memory cell and a method of forming the same are provided. A portion of a floating gate is formed on walls of a trench formed on the substrate. An inside of the trench is filled with a gate electrode layer constituting a sensing line. This leads to increases in opposite areas of a floating gate and a control gate of a sensing transistor, and a decrease in an area of the floating gate in the substrate. The method of forming an EEPROM memory cell comprises forming a trench in an active area in which a sensing transistor of the substrate will be formed; forming a gate insulation layer including a tunneling insulation layer on an entire surface of the substrate including an inside of the trench; conformally forming a first conductive layer covering the inside of the trench after forming the gate insulation layer; conformally forming a dielectric layer on the first conductive layer; forming a floating gate by patterning the first conductive layer; and stacking and patterning a second conductive layer on the dielectric layer to form a word line and a sensing line.

REFERENCES:
patent: 4796228 (1989-01-01), Baglee
patent: 5049515 (1991-09-01), Tzeng
patent: 5315142 (1994-05-01), Acovic et al.
patent: 5429970 (1995-07-01), Hong
patent: 5486714 (1996-01-01), Hong
patent: 5932910 (1999-08-01), Hong
patent: 6232632 (2001-05-01), Liu

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