EEPROM device having an isolation-bounded tunnel capacitor...

Details EEPROM device having an isolation-bounded tunnel capacitor... EEPROM device having an isolation-bounded tunnel capacitor...

2005-01-11

2005-01-11

Booth, Richard A. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S296000

Reexamination Certificate

active

06841447

ABSTRACT:
A semiconductor device having an EEPROM memory cell includes a substrate having a principal surface and an isolation region having an inner edge surface bounding the tunnel region at the principal surface. The isolation region forms a perimeter of the tunnel region. A capacitor plate overlies the tunnel region and substantially the entire perimeter of the tunnel region. A tunnel dielectric layer overlies the tunnel region and separates the capacitor plate from the tunnel dielectric layer. The edges of the capacitor plate are displaced away from the tunnel dielectric layer to avoid a loss of tunneling current as a result of edge degradation with repeated programming and erasing of the EEPROM memory device. A process for fabrication of the device is also provided.

REFERENCES:
patent: 4924278 (1990-05-01), Logie
patent: 6365457 (2002-04-01), Choi
patent: 6410389 (2002-06-01), Cappelletti et al.
patent: 6613631 (2003-09-01), Koishikawa

Affiliated with

Also associated with

Rating

EEPROM device having an isolation-bounded tunnel capacitor... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with EEPROM device having an isolation-bounded tunnel capacitor..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and EEPROM device having an isolation-bounded tunnel capacitor... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3419668