Static information storage and retrieval – Read/write circuit – Precharge
Patent
1981-04-15
1983-06-07
Stellar, George G.
Static information storage and retrieval
Read/write circuit
Precharge
G11C 700
Patent
active
043874487
ABSTRACT:
Disclosed is a dynamic semiconductor memory device with decreased clocks having a pull up circuit associated with a pair of bit lines. The pull up circuit comprises a pair of first switching transistors connected between a power supply line and the associated bit line, and, a pair of second switching transistors. Each gate of the second switching transistors is connected to the bit line of opposite side. The turning on or off of the second switching transistor controls the gate potential of the first switching transistor.
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IBM Technical Disclosure Bulletin, vol. 17, No. 9, Feb. 1975, pp. 2582-2583, Low-Power, High-Speed Sense Latch, Chu et al.
1979 IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 140-141, Dynamic Memories-The Design of MOS Dynamic Rams, Foss.
1980 IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 66-67, Digital Circuit Techniques-A Stacked High Capacitor Ram, Ohta et al.
Mezawa Tsutomu
Nozaki Shigeki
Takemae Yoshihiro
A. Aoki & Associates
Stellar George G.
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