Static information storage and retrieval – Read/write circuit – Precharge
Reexamination Certificate
1999-07-13
2001-03-20
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Precharge
C365S207000
Reexamination Certificate
active
06205068
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly to a dynamic random access memory device with a divided precharge control scheme capable of realizing high-speed access with a low power supply voltage.
2. Description of the Related Art
As the integration densities of semiconductor memory devices continues to increase, there is a continuing need to reduce the power supply voltages to the semiconductor memory devices to, among other things, minimize total power consumption and compensate for the smaller sizes of the discrete devices therein. In particular, in order to scale the size of MOS devices contained on a memory integrated circuit (IC), it is typically necessary to reduce the thickness of the gate oxide and the line widths of the gate electrodes and other interconnect lines connected to the MOS devices. Moreover, to achieve reliable operation of such reduced size devices, it is necessary to reduce the voltages at which these devices operate.
For example, in a 256-Mb dynamic random access memory (DRAM), it is typically necessary to reduce the external power supply voltage of about 3.3 volts, which is applied to the memory IC, to an internal voltage of about 1.5 volts (i.e., IVC=1.5 volts) in order to obtain reliable operation. However, as will be understood by those skilled in the art, decreasing the operating voltage typically reduces the sensing, amplification, and drive capability of sense amplifiers used to sense data stored in memory cell and limits the degree to which the sense amplifiers can adequately refresh memory cells after a read operation.
FIG. 1
shows the structure of a memory cell array and the peripheral circuits required for read and write operations in a conventional dynamic random access memory device. Each memory cell MC includes an access transistor
10
which serves as a switch, and a capacitor
12
which holds a bit of data. The gates of the access transistors
10
which are arranged in the same row are connected to a common word line WLi, where i=(1, 2, 3, . . . , n). The sources of the access transistors
10
which are arranged in a column are connected to alternate lines of a bit line pair BLj and BLjB, where j=(1, 2, . . . , m). One electrode of each capacitor
12
is connected to the drain of the corresponding access transistor
10
, while the other electrode is connected to receive a plate voltage V
P
.
When a row address is supplied, it is decoded by a row decoder
14
into a row address signal, and one word line corresponding to the decoded row address is activated, thus turning on all the access transistors
10
connected to the activated word line. The stored charge on all the capacitors
12
corresponding to the activated word line flow onto the bit lines coupled to the capacitors
12
. Owing to the relatively low capacitance of the capacitors
12
used in the memory device, sense amplifier circuits
16
are used to amplify the slight effect which the capacitor has on the bit line pair. Each of the sense amplifier circuits
16
draws the potential of the bit line having the lowest voltage to VSS, and raises the potential of the bit line having the higher voltage up to IVC. Only one of the amplified signals passes through the I/O gate circuit
20
corresponding to a decoded column address from column decoder
18
.
FIG. 2
is a circuit diagram of a conventional sense amplifier circuit
16
associated with one of the memory cells of FIG.
1
. Sense amplifier circuit
16
includes a pair of bit lines BL and BLB, a bit line equalization circuit
26
, a sense amplifier
28
, a column select gate
30
, a sense amplifier equalization circuit
32
, and a sense amplifier activating circuit
34
. The bit lines BL and BLB, to which data is transferred, are connected to the memory cell MC. Each memory cell MC has an access transistor
10
coupled to a word line and a bit line, and a capacitor
12
coupled between the access transistor
10
and the plate voltage V
P
.
The bit line equalization circuit
26
receives a precharge voltage VBL and equalizes the bit lines BL and BLB to the precharge voltage level before a read operation or a write operation is performed. The sense amplifier
28
differentially amplifies the data transferred from the memory cell MC to the bit lines BL and BLB. The column select gate
30
connects the bit lines BL and BLB to the input/output lines IO and IOB in response to the column select line signal CSL. The sense amplifier equalization circuit
32
equalizes the sense amplifier nodes to the precharge voltage VBL. Once equalized, P-type sense amplifier and N-type sense amplifier latch enable signals LA and LAB, which control the sense amplifier
28
, are activated as a result of the sense amplifier activating circuit
34
, which is connected to the sense amplifier equalization circuit
32
and receives the sense amplifier activating signal LAPG and LANG.
The bit line equalization circuit
26
has three NMOS transistors M
1
, M
2
and M
3
connected between the bit lines BL and BLB. The transistors M
1
, M
2
and M
3
have gate electrodes for receiving a bit line equalization signal PEQ. Further, the precharge voltage VBL is input to the source electrodes of the NMOS transistors M
1
and M
2
. The sense amplifier
28
is comprised of a P-type sense amplifier and an N-type sense amplifier. The P-type sense amplifier has PMOS transistors M
4
and M
5
which are connected in series between the bit lines BL and BLB. The P-type sense amplifier latch enable signal LA is input to the commonly connected source electrodes of the PMOS transistors M
4
and M
5
, with the gate electrodes of the PMOS transistors M
4
and M
5
connected to the bit lines BL and BLB, respectively. The N-type sense amplifier has two NMOS transistors M
6
and M
7
connected in series to the bit lines BL and BLB. The N-type sense amplifier latch enable signal LAB is input to the commonly connected source electrodes of the NMOS transistors M
6
and M
7
. The gates of transistors M
6
and M
7
are connected to the bit lines BL and BLB, respectively.
The column select gate
30
has two NMOS transistors M
8
and M
9
whose gate electrodes are coupled to the column select line CSL. The transistors M
8
and M
9
connect the bit lines BL and BLB to the input/output lines IO and IOB under control of the column select line CSL. The sense amplifier equalization circuit
32
has three NMOS transistors M
10
, M
11
and M
12
whose gate electrodes are collectively connected to a latch enable equalization signal PLAEQ. The sense amplifier activating circuit
34
has PMOS and NMOS transistors M
13
and M
14
. The PMOS transistor M
13
has its gate electrode connected to a P-type sense amplifier activating signal LAPG and its current path formed between the signal line LA and the internal power supply voltage IVC. The NMOS transistor M
14
whose gate electrode is connected to a N-type sense amplifier activating signal LANG, has its current path formed between the signal line LAB and VSS.
FIG. 3A
is an example of the bit line equalization signal generator
22
illustrated in FIG.
1
. The bit line equalization signal generator
22
as shown in
FIG. 3A
has a PMOS transistor M
15
and an NMOS transistor M
16
which are connected in series between the internal power supply voltage IVC and the ground voltage VSS and have their gate electrodes commonly connected to a control signal PBLS. The bit line equalization signal PEQ is maintained at the level of the ground voltage VSS or the internal power supply voltage IVC according to the logic level of the control signal PBLS.
FIG. 3B
is an example of the latch enable equalization signal generator
24
illustrated in FIG.
1
. The latch enable equalization signal generator
24
has a PMOS transistor M
17
and an NMOS transistor M
18
which are connected in series between the internal power supply voltage IVC and the ground voltage VSS. The gate electrodes of the transistors M
17
and M
18
are commonly connected to the co
Marger & Johnson & McCollom, P.C.
Nguyen Tan T.
Samsung Electronics Co,. Ltd.
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