Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-10-23
2001-01-16
Whitehead, Jr., Carl (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S254000, C438S396000, C438S397000
Reexamination Certificate
active
06174768
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device, and more particularly to a dynamic random access memory cell having an improved fin-structured storage electrode and a method of fabricating the same.
Generally, the dynamic random access memory cell has a pair of a transfer field effect transistor and a memory cell capacitor. This simple structure of the dynamic random access memory cell is suitable for high integration of the dynamic random access memory device. There has been developed a memory cell capacitor having a three dimensional structure for further increase in the density of the integration of the memory cell array in the dynamic random access memory device.
Namely, in the light of the scale reduction of the memory cell and increase in the density of the integration of the memory cell array, it is required to reduce an occupied area of the memory cell capacitor and ensure a large capacitance necessary for allowing the dynamic random access memory device to show stable operations and has a reliance on operations thereof, for the purpose of which it is further necessary to increase in surface area of a memory cell capacitor storage electrode as much as possible.
The three dimensional structured memory cell capacitor is classified into two types. First one is the stacked memory cell capacitor and second one is the trench memory cell capacitor. The stacked memory cell capacitor has a high resistivity to noises due to alpha-ray incidence or circuits, for which reason the stacked memory cell capacitor is capable of performing stable operations even if the capacitance of the stacked memory cell capacitor is relatively small. Generally, it seems considered that the stacked memory cell capacitor is available to 0.15 micrometers scale rule for 1 Gbit dynamic random access memory device.
As one of the stacked memory cell capacitors, various fin-structured memory cell capacitors have been proposed and, for example, disclosed in INTERNATIONAL ELECTRON DEVICES MEETING, 1988 pp. 593-595, entitled “3-DIMENSIONAL STACKED CAPACITOR CELL FOR 16M AND 64M DRAMS”, and also disclosed in the Japanese laid-open patent publication No. 5-291524. The fin-structure is effective to increase the surface area of the memory cell capacitor storage electrode. In order to obtain a further increase in the surface area of the fin-structured storage electrode of the stacked memory cell capacitor, it is effective to increase the number of fins of the storage electrode. Since each fin comprises a conductive layer, if the number of the fines of the storage electrode is increased, then the mechanical strength of the fin structure of the storage electrode of the memory cell capacitor is reduced whereby the conductive film forming each fin may be curved. As a result, the reliability of performances of the fin structured storage electrode of the stacked memory cell capacitor is reduced. In the Japanese laid-open patent publication No. 5-291524, it is disclosed to strengthen the fin structure of the storage electrode of the memory cell capacitor. The fin-structured storage electrode of the stacked memory cell capacitor may be fabricated in accordance with a method to be described below with reference to
FIGS. 1A through 1E
which are fragmentary cross sectional elevation views illustrative of a conventional fin-structured storage electrode of the stacked memory cell capacitor.
With reference to
FIG. 1A
, a first silicon oxide film
52
is formed as an inter-layer insulator over a silicon substrate
51
. A first silicon nitride film
53
is formed over the first silicon oxide film
52
. The first silicon nitride film
53
will serve as an etching stopper to etchant of hydrofluoric acid in later process to be described below. A second silicon oxide film
54
is formed over the first silicon nitride film
53
. A second silicon nitride film
55
is then formed over the second silicon oxide film
54
. A first polysilicon film
56
is then formed over the second silicon nitride film
55
. A third silicon oxide film
57
is formed over the first polysilicon film
56
. A third silicon nitride film
58
is further formed over the third silicon oxide film
57
. A second polysilicon film
59
is then formed over the third silicon nitride film
58
. A fourth silicon oxide film
60
is then formed over the second polysilicon film
59
. A fourth silicon nitride film
61
is then formed over the fourth silicon oxide film
60
.
With reference to
FIG. 1B
, a contact hole
62
is formed, which vertically extends from the fourth silicon nitride film
61
to the first silicon oxide film
52
so that a part of the silicon substrate
51
is shown through the contact hole
62
.
With reference to
FIG. 1C
, a third polysilicon film
63
is entirely formed over the fourth silicon nitride film
61
and within the contact hole
62
so that the silicon substrate
51
is made into contact with the polysilicon film
63
.
With reference to
FIG. 1D
, the laminations of the second silicon nitride film
55
, the first polysilicon film
56
, the third silicon oxide film
57
, the third silicon nitride film
58
, the second polysilicon film
59
, the fourth silicon oxide film
60
, the fourth silicon nitride film
61
and the third polysilicon film
63
are subjected to an anisotropic etching to pattern the same.
With reference to
FIG. 1E
, by use of a hydrofluoric acid solution is used to carry out a wet etching or an isotropic etching to etching the second silicon oxide film
54
, the third silicon oxide film
57
and the fourth silicon oxide film
60
, wherein the first silicon nitride film
53
, the second silicon nitride film
55
, the third silicon nitride film
58
and the fourth silicon nitride film
61
serve as etching stoppers thereby to form a fin-structured storage capacitor electrode
64
over the silicon substrate
51
. The first polysilicon film
56
serves as a first conductive layer of the fin-structured storage capacitor electrode
64
. The first conductive layer is supported by the second silicon nitride film
55
. The second polysilicon film
59
serves as a second conductive layer of the fin-structured storage capacitor electrode
64
. The second conductive layer is supported by the third silicon nitride film
58
. The third polysilicon film
63
serves as a third conductive layer of the fin-structured storage capacitor electrode
64
. The third conductive layer is supported by the fourth silicon nitride film
61
. In this case, the fin-structured storage electrode has three fins. Notwithstanding, it is possible to increase the number of fins of the fin-structured storage electrode in order to increase the surface area of the fin-structured storage electrode.
As described above, the second silicon nitride film
55
, the third silicon nitride film
58
and the fourth silicon nitride film
61
serve as the supporting layers for supporting the three fins of the first, second and third conductive layers of the fin-structured storage electrode in order to prevent the three fins of the first, second and third conductive layers from being curved or bent to contact with each other. However, the supporting layers of the second, third and fourth silicon nitride films
55
,
58
and
61
make it difficult to reduce the thickness of a capacitive insulation film covering the fin-structured storage electrode. The reduction in the thickness of the capacitive insulation film of the fin-structured storage electrode is essential to increase the capacitance of the fin-structured storage electrode, for which reason the difficulty in reduction in the thickness of the capacitive insulation film of the fin-structured storage electrode makes it difficult to increase the capacitance of the fin-structured storage electrode.
In order to settle the above problem, it is required to remove the second, third and fourth silicon nitride films
55
,
58
and
61
by a wet etching or an isotropic etching. Since the etching rate of the silicon nitride film is low, a relatively long time is necessary for removal of
Jr. Carl Whitehead
NEC Corporation
Thomas Janice M.
Young & Thompson
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