Dynamic precharge decode scheme for fast DRAM

Details Dynamic precharge decode scheme for fast DRAM Dynamic precharge decode scheme for fast DRAM

2001-08-01

2003-01-21

Lam, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Precharge

C365S230030, C365S230060

Reexamination Certificate

active

06510091

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention generally relates to a dynamic global precharge decode scheme for dynamic random access memory (DRAM), and more specifically to a DRAM decode scheme which includes a dynamic global precharge signal generated based on a sense amplifier set signal.
2. Description of the Related Art
DRAM memory chip systems typically have a number of units or blocks, including a first set of address generators which identify a word and a column address, second set of address generators, further referenced as RACP generators, which identify a subarray address, a number of subarrays which include a number of cells for storing data, and wiring to interconnect the various units. Signals propagate from one block to the next, such that an exit signal from a first block activates a second block.
The DRAM chips operation can be broken into two parts: an active phase, and a precharge phase. Signal transitions associated with the active phase will be referred to as active phase transitions, while those associated with the precharge phase will be referred to as precharge phase transitions.
Active phase transitions provide address and other information to a chip and causes the execution of an operation. This operation results in either a logical state being sensed from a particular cell or a particular cell being set to a high/low logical state. The active phase signal transition travels along one or more busses, such as a word/column address bus and a RACP address bus. Precharge phase transitions place the chip in a state to receive a subsequent active phase signal.
In order for the read or write operation to be successful, there must be a sufficiently long period of time between the active phase transition and the precharge phase transition, hereinafter the active signal period. However, the longer the active signal period, the slower the DRAM cycle time. Conventional static random access memory (SRAM) systems have addressed these opposite requirements of fast cycle times and long active signal duration through local and global precharging, as disclosed in U.S. Pat. No. 4,845,677, invented by Chappell et al, and assigned to International Business Machines Corporation. However, a DRAM system using a dynamic precharge signal has heretofore not been taught.
Furthermore, the conventional systems do not teach a precharge activation path matched to the address decode path, such that all cells have the same active signal period. Additionally, the conventional systems do not teach a DRAM system optimized for the active phase transition as opposed to the precharge phase transition (e.g., optimized in the forward direction), such that the active transition races through the address decode path thereby maximizing the active signal period.
SUMMARY OF THE INVENTION
In view of the above and other problems of the conventional systems and techniques, it is an object of the present invention to provide a DRAM which uses a dynamic precharge system.
It is another object of the invention to provide a DRAM in which a dynamic global precharge activation path and an address decode path are matched and a method for operating the same.
It is a further object of the invention to provide a system and method for optimizing an address path in a forward direction to gain an improvement in access time.
It is a further object of the invention to provide a system and method for providing a global decode scheme without the use of address latching by a Macro Select Not (MSN) signal.
It is a still further object of the invention to simplify a DRAM by using a single signal to activate the precharge phase of both a RACP generator and an address generator.
It is a still further object of the invention to enable a two-fold strategy for timing a start of a precharge, wherein a first strategy includes a self-timed strategy wherein the sense amplifier activation signal SETP signal triggers a precharge activation and a second strategy includes a clock-controlled strategy for conducting a margin test.
According to one embodiment of the invention, these and other objects are achieved by a DRAM including first address generators which identify a word and a column address, second address or RACP generators which identify a subarray address, a number of subarrays which include a number of cells for storing data, an address decode path configured to transmit address and other information, and a precharge activation path configured to transmit a precharge activation signal, wherein the precharge activation path and the address decode path are matched.
In a second aspect, a method includes initiating a sense amplifier signal after initiation of a word line selection signal, initiating a subarray precharge signal after initiation of the sense amplifier signal, wherein the subarray precharge signal path is matched with a subarray selection signal path, and initiating a word/column precharge signal after initiation of the sense amplifier signal, wherein the word/column precharge signal path is matched with the word/column selection signal path.
With the unique and non-obvious aspects of the present invention, it is an object of the present invention to provide a DRAM which uses a dynamic precharge system. It is another object of the invention to provide a DRAM in which a dynamic global precharge activation path and an address decode path are matched and a method for operating the same.
It is a further object of the invention to provide a system and method for optimizing an address path in a forward direction to gain an improvement in access time.


REFERENCES:
patent: 4845677 (1989-07-01), Chappell et al.
patent: 5424990 (1995-06-01), Ohsawa
patent: 5542067 (1996-07-01), Chappell et al.
patent: 5936873 (1999-08-01), Kongetira
patent: 6233195 (2001-05-01), Yamazaki et al.

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