Dynamic logic circuit including dynamic standard cell library

Electronic digital logic circuitry – Significant integrated structure – layout – or layout... – Field-effect transistor

Reexamination Certificate

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Details

C326S095000, C326S098000

Reexamination Certificate

active

07961010

ABSTRACT:
A dynamic logic circuit includes a first region including a plurality of PMOS transistors and a second region, adjacent to the first region, including a plurality of NMOS transistors connected with at least one of the plurality of PMOS transistors. Channel sizes of the plurality of NMOS transistors are greater than channel sizes of the plurality of PMOS transistors.

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English Abstract for Publication No. 1020080040557.

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