Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
1999-03-04
2001-07-10
Smith, Matthew (Department: 2825)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
C257S170000, C257S354000
Reexamination Certificate
active
06259115
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to the manufacture of semiconductors and more specifically to improving planarity in semiconductor processes.
BACKGROUND ART
While manufacturing integrated circuits, after the individual devices, such as the transistors, have been fabricated in the silicon substrate, they must be connected together to perform the desired circuit functions. This connection process is generally called “metalization”, and is performed using a number of different photolithographic and deposition techniques.
One metalization process, which is called the “damascene” technique, starts with the placement of a first channel dielectric layer, which is typically an oxide layer, over the semiconductor devices. A first damascene step photoresist is then placed over the oxide layer and is photolithographically processed to form the pattern of the first channels. An anisotropic oxide etch is then used to etch out the channel oxide layer to form the first channel openings. The first damascene step photoresist is stripped. An optional thin adhesion layer of barrier material is deposited to coat the walls of the first channel opening to ensure good adhesion and electrical contact of subsequent layers to the underlying semiconductor devices. A barrier layer is then deposited on the adhesion layer to improve the formation of subsequently deposited conductive material and to act as a barrier material to prevent diffusion of such conductive material into the oxide layer and the semiconductor devices (the combination of the adhesion and barrier material is collectively referred to as “barrier layer” herein). It should be noted that some barrier materials also have good adhesion, which is why the adhesion layer is optional. A “seed” layer is then deposited to act as a seed for additional conductive material to be deposited. A first conductive material is then deposited. For deposition of the adhesion, barrier, seed, and conductive materials, the deposition processes require uniform heating of the silicon substrate. These materials are then subjected to a planarizing chemical-mechanical polishing (CMP) process which removes the layers of material above the first channel oxide layer and damascenes the first conductive material in the first channel openings to form the first channels.
For multiple layers of channels, another metalization process, which is called the “dual damascene” technique, is used in which the channels and vias are formed at the same time. In one example, the via formation step of the dual damascene process starts with the deposition of a thin stop nitride over the first channels and the first channel oxide layer. Subsequently, a separating oxide layer is deposited on the stop nitride. This is followed by deposition of a thin via nitride. Then a via step photoresist is used in a photolithographic process to designate round via areas over the first channels.
A nitride etch is then used to etch out the round via areas in the via nitride. The via step photoresist is then removed, or stripped. A second channel dielectric layer, which is typically an oxide layer, is then deposited over the via nitride and the exposed oxide in the via area of the via nitride. A second damascene step photoresist is placed over the second channel oxide layer and is photolithographically processed to form the pattern of the second channels. An anisotropic oxide etch is then used to etch the second channel oxide layer to form the second channel openings and, during the same etching process to etch the via areas down to the thin stop nitride layer above the first channels to form the via openings. The damascene photoresist is then removed, and a nitride etch process removes the nitride above the first channels in the via areas. An adhesion layer is then deposited to coat the via openings and the second channel openings. Next, a barrier layer is deposited on the adhesion layer. This is followed by a deposition of the second conductive material in the second channel openings and the via openings to form the second channel and the via. Again, for these deposition processes the silicon substrate should be uniformly heated. A second planarizing chemical mechanical polishing process leaves the two vertically separated, horizontally perpendicular channels connected by cylindrical vias.
The use of the damascene techniques eliminates metal etch and dielectric gap fill steps typically used in the conventional metalization process. The elimination of metal etch steps is important as the semiconductor industry moves from aluminum to other metalization materials, such as copper, which are very difficult to etch.
At the same time, there are a number of drawbacks to the damascene and dual damascene processes which are due to the generally uneven distribution of the pattern of the conductive channels. Often, there are many channels in one location and few in others. This means that during the chemical-mechanical-polishing processes, the areas where there are many channels tends to be relatively planar while those areas with fewer channels tend to be less planar, or dished out, because the dielectric is more easily polished than the conductive material. In addition, the irregular spacing of the channels adversely affects the spin-on deposition processes, such as those often used for the dielectric depositions in Al based metalizations. The drawbacks of the damascene and dual damascene technique have long plagued the industry.
Also, when the various deposition steps are being performed, after the first channels had been deposited, it is desirable that the temperature of the silicon substrate be uniform. However, the conductive material in the non-uniformly placed channels tends to cause irregular heating, which is detrimental to the deposition processes.
As the industry moves to smaller and smaller device sizes and harder materials than aluminum, it has become more critical that answers be found to these problems.
DISCLOSURE OF THE INVENTION
The present invention provides a technique of inserting dummy conductive channels by a weight-balancing technique to have an approximately even metal weight distribution across the silicon substrate.
The present invention provides for inserting dummy conductive channels to improve conductive material plating uniformly.
The present invention further provides for the insertion of dummy conductive channels to reduce chemical-mechanical-polishing dishing and thereby improving polishing planarity.
The present invention further provides for the insertion of dummy conductive material channels to improve heating uniformity for chemical and physical vapor deposition processes.
The present invention further provides for the insertion of dummy conductive channels on a silicon substrate to improve spin-on process properties.
The present invention further provides for the insertion of dummy conductive material channels to improve etch and photolithography uniformity.
The above and additional advantages of the present invention will become apparent to those skilled in the art from a reading of the following detailed description when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 5598010 (1997-01-01), Uematsu
patent: 5625232 (1997-04-01), Numata et al.
patent: 5994179 (1999-11-01), Masuoka
Chan Simon S.
Yang Kai
You Lu
Advanced Micro Devices , Inc.
Ishimaru Mikio
Smith Matthew
Yevsikov V.
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