Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-02-16
2001-05-08
Smith, Matthew (Department: 2825)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S410000, C257S411000, C438S257000, C438S299000, C438S766000
Reexamination Certificate
active
06229184
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a semiconductor device suitable for high speed performance. The present invention is particularly applicable for ultra large scale integration semiconductor devices having a design rule of abut 0.18 micron and under.
1. Background Art
The escalating requirements for high density and performance associated with ultra large scale integration semiconductor devices have been found difficult to satisfy in terms of providing a low RC (resistance capacitance) interconnection pattern. High performance microprocessor applications require rapid speed of semiconductor circuitry. The speed of semiconductor circuitry various inversely with the resistance and capacitance of the interconnection pattern. As design rules are reduced to about 0.18 micron and below, e.g., about 0.15 micron and below, the rejection rate due to integrated circuit speed delays severely limits production throughput and significantly increases manufacturing costs.
Conventional integrated circuits are limited in speed by a high capacitance load. When the high capacitance load becomes apparent in the “OFF” state, it is a clear indication that the source and drain capacitance significantly contribute to the total capacitance. Of the two, source capacitance and drain capacitance, the latter is the one that will mostly limit the circuit speed in the “ON” state. Therefore, it is highly desirable to limit the value of the drain capacitance.
There is, therefore, a need for a semiconductor device and enabling methodology wherein the gate oxide thickness is reduced to enable reduction of the drain capacitance without creating reliability problems.
2. Disclosure of the Invention
An advantage of the present invention is a semiconductor device comprising a transistor exhibiting reduced drain capacitance and a gate oxide layer with high reliability.
Another advantage of the present invention is a method of manufacturing a semiconductor device comprising a transistor with reduced drain capacitance and a gate oxide layer with high integrity.
Additional advantages and other features of the present invention will be set forth in the description which follows and in part will be apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a semiconductor device containing a transistor, the transistor comprising: a gate dielectric layer having first and second side surfaces on a substrate with a channel region therebetween; source and drain regions in the substrate with the channel region therebetween, the drain region formed proximate the first side surface and the source region formed proximate the second side surface; and a gate electrode on the gate dielectric layer, wherein the gate dielectric layer has a thickness at the first side surface which is less than its thickness at the second side surface.
Another aspect of the present invention is a method of manufacturing a semiconductor device, the method comprising: forming a gate dielectric layer on a substrate surface, the gate dielectric layer having first and second side surfaces and a thickness at the first side surface which is less than its thickness at the second side surface; forming a gate electrode layer on the gate dielectric layer; and forming source and drain regions in the semiconductor substrate with a channel region therebetween underlying the gate dielectric layer, the drain region formed proximate the first side surface and the source region formed proximate the second side surface.
Embodiments of the present invention include a semiconductor device comprising a transistor with a gate oxide layer having a thickness which gradually increases from proximate the drain region to proximate the source region, and a gate oxide having a first uniform thickness and a second uniform thickness greater than the first uniform thickness with a gradually increasing the transition zone between the first thickness and the second thickness. Embodiments of the present invention also include thermally oxidizing a substrate surface to form a gate oxide layer having a modulated thickness by ion implanting neutral impurities, such as silicon, argon or germanium, to increase the substrate surface oxidation rate proximate the contemplated source region and/or ion implanting nitrogen into the substrate surface to reduce the oxidation rate proximate the contemplated drain region.
Additional advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein embodiments of the present invention are described, simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be realized, the present invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.
REFERENCES:
patent: 5949117 (1999-09-01), Sandhu et al.
patent: 6077749 (2000-06-01), Gardner et al.
Advanced Micro Devices , Inc.
Anya Igwe U.
Smith Matthew
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