Dual strain-state SiGe layers for microelectronics

Details Dual strain-state SiGe layers for microelectronics Dual strain-state SiGe layers for microelectronics

2006-08-15

2006-08-15

Picardat, Kevin M. (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S285000, C438S481000

Reexamination Certificate

active

07091095

ABSTRACT:
A strained crystalline layer having a tensilely strained SiGe portion and a compressively strained SiGe portion is disclosed. The strained crystalline layer is epitaxially bonded, or grown, on top of a SiGe relaxed buffer layer, in a way that the tensilely strained SiGe has a Ge concentration below that of the SiGe relaxed buffer, and the compressively strained SiGe has a Ge concentration above that of the SiGe relaxed buffer. The strained crystalline layer and the relaxed buffer can reside on top a semi-insulator substrate or on top of an insulating divider layer. In some embodiments the tensile SiGe layer is pure Si, and the compressive SiGe layer is pure Ge. The tensilely strained SiGe layer is suited for hosting electron conduction type devices and the compressively strained SiGe is suited for hosting hole conduction type devices. The strained crystalline layer is capable to seed an epitaxial insulator, or a compound semiconductor layer.

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