Dual power sensing scheme for a memory device

Details Dual power sensing scheme for a memory device Dual power sensing scheme for a memory device

2005-05-03

2005-05-03

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Precharge

C365S204000, C365S207000, C365S226000

Reexamination Certificate

active

06888767

ABSTRACT:
Sensing operations involving a first array of bit line sense amplifiers (BLSAs) may be powered by an upper reference voltage and a first intermediate voltage and the first array may be precharged to a voltage level therebetween. Sensing operations involving a second array of BLSAs may be powered by a second intermediate voltage (greater than the first intermediate voltage) and a lower reference voltage and the second array may be precharged to a voltage level therebetween. After precharge, charge may be transferred from a second power line of the first array to a first power line of the second array. Subsequently, the second power line of the first array may be coupled to a power supply node at the first intermediate voltage level and the first power line of the second array may be coupled to a power supply node at the second intermediate voltage level.

REFERENCES:
patent: 6011738 (2000-01-01), Son et al.
patent: 6023437 (2000-02-01), Lee

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