Dual hard mask layer patterning method

Details Dual hard mask layer patterning method Dual hard mask layer patterning method

2003-04-30

2004-07-20

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S301000, C438S586000

Reexamination Certificate

active

06764903

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to methods for forming patterned layers within microelectronic products. More particularly, the invention relates to methods for forming uniformly patterned layers within microelectronic products.
2. Description of the Related Art
Semiconductor products commonly employ field effect transistor devices as switching devices within logic products, memory products and embedded logic and memory products.
While field effect transistor devices are common within semiconductor products, they are nonetheless not entirely without problems. As semiconductor product integration levels increase and semiconductor device dimensions decrease, it becomes more difficult to form semiconductor devices with diminished dimensions and enhanced dimensional control. Since a gate electrode with a field effect transistor device defines a channel width and operational characteristics of the field effect transistor device, gate electrode linewidth control within semiconductor products is particularly important.
The present invention is thus directed towards forming patterned layers, such as gate electrodes, of diminished dimensions and enhanced dimensional control.
Various methods have been disclosed for forming patterned layers within microelectronic products.
Included but not limiting are methods disclosed within: (1) Tao et al., in U.S. Pat. No. 6,174,818 (a bilayer hard mask layer method for forming a gate electrode with enhanced dimensional control); (2) Foote et al., in U.S. Pat. No. 6,248,635 (a bilayer hard mask layer method for forming a metal-oxide-nitride-oxide-semiconductor (MONOS) structure with enhanced reliability); and (3) Liu et al., in U.S. Pat. No. 6,429,067 (a bilayer hard-mask layer method for forming gate electrodes of differing linewidths).
The disclosures of the foregoing references are incorporated herein fully by reference.
Desirable are additional methods for forming patterned layers with diminished dimensions and enhanced dimensional control within microelectronic products.
The present invention is directed toward the foregoing object.
SUMMARY OF THE INVENTION
A first object of the invention is to provide a method for forming a patterned layer within a microelectronic product.
A second object of the invention is to provide a method in accord with the first object of the invention, wherein the patterned layer is formed with diminished dimensions and enhanced dimensional control.
In accord with the objects of the invention, the invention provides a method for forming a patterned layer within a microelectronic product.
The method employs a substrate having formed thereover: (1) a blanket target layer, having formed thereupon; (2) a blanket first hard mask layer, having formed thereupon; (3) a blanket second hard mask layer, in turn having formed thereover; (4) a patterned third mask layer. Within the invention, the blanket second hard mask layer is first anisotropically etched within a first etchant to form a patterned second hard mask layer and then isotropically etched within a second etchant to form an isotropically etched patterned second hard mask layer of linewidth less than the patterned second hard mask layer. The isotropically etched patterned second hard mask layer is then used an etch mask with a third etchant for forming a patterned first hard mask layer from the blanket first hard mask layer. The patterned first hard mask layer is then used as an etch mask with a fourth etchant for forming a patterned target layer from the blanket target layer.
The method is particularly useful for forming gate electrodes within field effect transistor devices within semiconductor products.
The invention provides a method for forming a patterned layer with diminished dimensions and enhanced dimensional control.
The invention realizes the foregoing object within the context of a four step etch method that employs a pair of blanket hard mask layers and a patterned third mask layer for forming a patterned target layer from a blanket target layer. Within the four step etch method, an upper lying blanket second hard mask layer is first anisotropically etched to form a patterned hard mask layer and then isotropically etched to form an isotropically etched patterned hard mask layer of linewidth less than the patterned hard mask layer. The isotropically etched patterned hard mask layer may then serve as an etch mask when anisotropically etching layers therebelow.


REFERENCES:
patent: 5258095 (1993-11-01), Nagata et al.
patent: 5718800 (1998-02-01), Juengling
patent: 6174818 (2001-01-01), Tao et al.
patent: 6248635 (2001-06-01), Foote et al.
patent: 6429067 (2002-08-01), Liu et al.
patent: 6605541 (2003-08-01), Yu
patent: 6607955 (2003-08-01), Lee

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