Dual gate and double poly capacitor analog process integration

Details Dual gate and double poly capacitor analog process integration Dual gate and double poly capacitor analog process integration

1999-04-26

2001-04-17

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S396000, C438S398000, C438S257000

Reexamination Certificate

active

06218234

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating an analog capacitor integrated circuit device, and more particularly, to a method of forming an analog capacitor integrated circuit device in which the double polysilicon capacitor and dual gate processes are combined.
2. Description of the Prior Art
Capacitors are critical components in the integrated circuit devices of today. For example, in analog integrated circuit devices, capacitors play an important role. High value resistors are not necessary in analog capacitor applications. Conventionally, the double poly capacitor process to make an analog capacitor and the dual gate process are separate modules. First, a thin gate oxide is formed, then the thick gate oxide is formed. The thick gate oxide formation typically involves two oxidation steps and photoresist stripping steps. The thick gate oxide resulting from this process may have poor integrity. After transistor formation, the capacitor process module is inserted, having capacitor dielectric and polysilicon depositions to form the capacitor plate and resistor. The additional thermal budget used for the capacitor and resistor will impact the transistors. It is desired to simplify the existing process and to modify the design for the polysilicon layer and capacitor mask so that the dual gate and double poly capacitor modules can be integrated in the analog capacitor process.
U.S. Pat. Nos. 5,843,817 to Lee et al and 5,858,831 to Sung teach logic and embedded memory integration methods. U.S. Pat. No. 5,668,035 to Fang et al teaches a dual gate process. U.S. Pat. No. 5,670,410 to Pan teaches fabrication of an analog capacitor using an oxide capacitor dielectric layer. None of these patents show the integration of dual gate and double poly capacitor processes for an analog capacitor integrated circuit device.
SUMMARY OF THE INVENTION
Accordingly, it is a primary object of the invention to provide an effective and very manufacturable process for fabricating an analog capacitor.
Another object of the present invention is to provide a method for integrating the dual gate and double poly capacitor processes to fabricate an analog capacitor integrated circuit device.
In accordance with the objects of this invention, a method for integrating the dual gate and double poly capacitor processes to fabricate an analog capacitor integrated circuit device is achieved. An isolation region is provided separating a first active area from a second active area in a semiconductor substrate. A first gate oxide layer is formed overlying the semiconductor substrate in the first and second active areas. A first polysilicon layer is deposited overlying the first gate oxide layer and the isolation region. An oxide layer is deposited overlying the first polysilicon layer. A nitride layer is deposited overlying the oxide layer. The nitride layer, oxide layer, and first polysilicon layer are etched away where they are not covered by a mask to form a first polysilicon gate electrode in the first area and to form a polysilicon capacitor bottom plate and overlying capacitor dielectric comprising the oxide and nitride layers overlying the isolation region. The first gate oxide layer is removed in the second area. A second gate oxide layer is formed in the second area wherein the second gate oxide layer has a thickness less than the thickness of the first gate oxide layer. A second polysilicon layer is deposited overlying the second gate oxide layer, bottom capacitor plate and capacitor dielectric, and the first polysilicon gate electrode. The second polysilicon layer is etched away where it is not covered by a mask to form a second polysilicon gate electrode in the second area and to form a top capacitor plate overlying the bottom capacitor plate having the capacitor dielectric layer therebetween.


REFERENCES:
patent: 5668035 (1997-09-01), Fang et al.
patent: 5670410 (1997-09-01), Pan
patent: 5843817 (1998-12-01), Lee et al.
patent: 5858831 (1999-01-01), Sung
patent: 5879983 (1999-03-01), Sewaga et al.
patent: 5953599 (1999-09-01), EltDiwany
patent: 6069036 (2000-05-01), Kim

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