Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2007-03-27
2007-03-27
Everhart, Caridad (Department: 2891)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C257SE21036
Reexamination Certificate
active
10933589
ABSTRACT:
A method for creating a hole in a semiconductor wafer includes forming a hard mask over a dielectric layer, the hard mask including a solid portion and a first opening. A patterning layer is provided over the hard mask, the patterning layer including second and third openings. The second opening of the patterning layer aligns with the first opening of the hard mask and the third opening of the patterning layer aligns with the solid portion of the hard mask. The hole is created in the dielectric layer using the second opening of the patterning layer and the first opening of the hard mask.
REFERENCES:
patent: 6664011 (2003-12-01), Lin et al.
patent: 6794293 (2004-09-01), Li et al.
patent: 2003/0091907 (2003-05-01), Horak et al.
patent: 2003/0104319 (2003-06-01), Lin et al.
patent: 2003/0170978 (2003-09-01), Lee
patent: 2004/0004290 (2004-01-01), Furukawa et al.
patent: 2004/0043618 (2004-03-01), Hellig et al.
patent: 2004/0161927 (2004-08-01), Hu et al.
Bergeron, David, “Resolution Enhancement Techniques for the 90-nm Technology Node and Beyond”, Future Fab International, www.future-fab.com, printed on Apr. 28, 2004, 10 pages.
Lucas, Kevin, “Achieving the 90nm Lithography Generation with Model-Based OPC”, Future Fab International, www. future-fab.com, printed on Apr. 28, 2004, 12 pages.
Mack, Chris A., et al., “Impact of Mask Errors on Optical Lithography”, Yield Management Solutions, Spring 2000, pp. 57-61.
Peterson, Bill, et al., “Approaches to Reducing Edge Roughness and Substrate Poisoning of ESCAP Photoresists”, www.semiconductorfabtech.com, printed on Apr. 28, 2004, 8 pages.
Pollentier, Ivan, et al., “Dual Damascene Back-end Patterning Using 248nm and 193nm Lithography”, Semiconductor Fabtech—13thedition, Mar. 2001, pp. 227-234.
Spence, Chris, “Mask Data Preparation Issues for the 90 nm Node: OPC Becomes a Critical Manufacturing Technology”, Future Fab International, www.future-fab.com, printed on Apr. 28, 2004, 7 pages.
Everhart Caridad
Haynes and Boone LLP
Taiwan Semiconductor Manufacturing Company , Ltd.
LandOfFree
Dual damascene process with dummy features does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Dual damascene process with dummy features, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dual damascene process with dummy features will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3759681