Dual damascene method employing sacrificial via fill layer

Details Dual damascene method employing sacrificial via fill layer Dual damascene method employing sacrificial via fill layer

1999-08-20

2002-03-26

Chaudhuri, Olik (Department: 2814)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S738000

Reexamination Certificate

active

06362093

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to methods for forming patterned layers within microelectronic fabrications. More particularly, the present invention relates to dual damascene methods for forming patterned layers within microelectronics fabrications.
2. Description of the Related Art
Microelectronic fabrications are formed from microelectronic substrates over which are formed patterned microelectronic conductor layers which are separated by microelectronic dielectric layers.
As microelectronic fabrication integration levels have increased, and microelectronic device and patterned microelectronic conductor layers dimensions have decreased, it has become increasingly common within the art of microelectronic fabrication to employ dual damascene methods for forming contiguous patterned conductor stud layer/patterned conductor interconnect layer layers within microelectronic fabrications. Such dual damascene methods are understood by a person skilled in the art to entail forming through a lower portion of a dielectric layer a via which accesses a contact region within a microelectronic layer formed beneath the dielectric layer, while also forming through an upper portion of the dielectric layer a trench which is contiguous with and larger than the via formed through the lower portion of the dielectric layer, prior to forming within the via and the contiguous trench a contiguous patterned conductor stud layer/patterned conductor interconnect layer while employing a single conductor material and while employing a single chemical mechanical polish (CMP) planarizing when forming the contiguous patterned conductor stud layer/patterned conductor interconnect layer.
Such dual damascene methods are desirable within the art of microelectronic fabrication, at least in part, since such dual damascene methods provide for microelectronic fabrication process efficiency when fabricating patterned conductor stud layers and patterned conductor interconnect layers within microelectronic fabrications.
While dual damascene methods are thus desirable within the art of microelectronic fabrication, dual damascene methods are nonetheless not entirely without problems in the art of microelectronic fabrication. In particular, it is often difficult to form within microelectronic fabrications patterned microelectronic dielectric layers which define contiguous vias and trenches into which are subsequently formed contiguous patterned conductor stud layer/patterned conductor interconnect layer layers, while defining the contiguous vias and trenches, and thus the contiguous patterned conductor stud layer/patterned conductor interconnect layer layers, with uniform and enhanced dimensional integrity.
It is thus towards the goal of providing within microelectronic fabrications dual damascene methods through which may be formed contiguous patterned conductor stud layer/patterned conductor interconnect layer layers with enhanced dimensional integrity that the present invention is directed.
Various dual damascene methods possessing desirable properties have been disclosed in the art of microelectronic fabrication.
For example, Shoda, in U.S. Pat. No. 5,529,953, discloses a dual damascene method for forming through a dielectric layer within a microelectronic fabrication a contiguous patterned conductor stud layer/patterned conductor interconnect layer with inhibited formation of seams and voids within the contiguous patterned conductor stud layer/patterned conductor interconnect layer. The dual damascene method employs: (1) a first seed material formed upon the floor of a via formed through the dielectric layer, into which via is formed a patterned conductor stud layer portion of the contiguous patterned conductor stud layer/patterned conductor interconnect layer; and (2) a second seed material formed upon the floor of a trench formed within the dielectric layer, into which trench is formed a patterned conductor interconnect layer portion of the contiguous patterned conductor stud layer/patterned conductor interconnect layer, where a conductor material from which is formed the contiguous patterned conductor stud layer/patterned conductor interconnect layer is formed more rapidly upon the first seed material than upon the second seed material.
In addition, Jain et al., in U.S. Pat. No. 5,741,626, disclose a method which may be employed for forming a dual damascene structure with enhanced dimensional integrity within a microelectronic fabrication while employing i-line and g-line photoexposure radiation when fabricating the dual damascene structure within the microelectronic fabrication. The method employs when fabricating the dual damascene structure at least one anti-reflective coating (ARC) layer formed of a dielectric tantalum nitride material, where the anti-reflective coating (ARC) layer may be formed in any of several locations when forming the dual damascene structure.
Further, Yew et al., in U.S. Pat. No. 5,801,094, disclose a dual damascene method for forming through a composite dielectric layer within a microelectronic fabrication a contiguous patterned conductor stud layer/patterned conductor interconnect layer with greater process latitude when forming the contiguous patterned conductor stud layer/patterned conductor interconnect layer through the composite dielectric layer within the microelectronic fabrication. The dual damascene method employs a patterned etch stop layer formed interposed between: (1) a lower dielectric layer within the composite dielectric layer, through which lower dielectric layer is formed a via into which is formed a patterned conductor stud layer portion of the contiguous patterned conductor stud layer/patterned conductor interconnect layer; and (2) an upper dielectric layer within the composite dielectric layer, through which upper dielectric layer is formed a trench contiguous with the via, into which trench is formed a patterned conductor interconnect layer portion of the contiguous patterned conductor stud layer/patterned conductor interconnect layer, wherein the trench and the via are etched employing a single plasma etch method which provides a tapered edge to an etched patterned etch stop layer formed from the patterned etch stop layer.
Finally, Kim et al., in U.S. Pat. No. 5,801,099, disclose a dual damascene method for forming through a dielectric layer within a microelectronic fabrication a contiguous patterned conductor stud layer/patterned conductor interconnect layer with inhibited etch damage to a conductor contact region accessed by a patterned conductor stud layer portion of the contiguous patterned conductor stud layer/patterned conductor interconnect layer. The dual damascene method employs a sacrificial via fill layer which defines the location of a via formed through a lower portion of the dielectric layer, the via being contiguous with a trench formed through an upper portion of the dielectric layer, where the sacrificial via fill layer is formed prior to forming the dielectric layer.
Desirable in the art of microelectronic fabrication are additional dual damascene methods for forming through a dielectric layer within a microelectronic fabrications a via contiguous with a trench, where the via contiguous with the trench is formed with enhanced dimensional integrity such that a contiguous patterned conductor stud layer/patterned conductor interconnect layer formed into the via contiguous with the trench is similarly also formed with enhanced dimensional integrity.
It is towards the foregoing object that the present invention is directed.
SUMMARY OF THE INVENTION
A first object of the present invention is to provide a dual damascene method for forming within a microelectronic fabrication a contiguous patterned conductor stud layer/patterned conductor interconnect layer.
A second object of the present invention is to provide a method in accord with the first object of the present invention, where the contiguous patterned conductor stud layer/patterned conductor interconnect layer is formed with enhanced

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