Static information storage and retrieval – Read/write circuit – Precharge
Reexamination Certificate
2001-08-09
2003-05-20
Dinh, Son T. (Department: 2524)
Static information storage and retrieval
Read/write circuit
Precharge
C365S204000, C330S009000, C330S053000, C330S054000, C330S255000
Reexamination Certificate
active
06567327
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a driving circuit, a charge/discharge circuit and the like for driving a capacitive load, and more particularly, to a driving circuit, a charge/discharge circuit and the like that are suitable for a liquid crystal display device and the like using an active matrix driving method.
In recent years, with development of communication technology, demand has increased for portable equipment with a display that includes a mobile phone, a personal digital assistant and the like. It is important for portable equipment to have sufficiently long continuous use, and a liquid crystal display device has been widely used for a display of portable equipment because of its low power consumption.
Further, although a liquid crystal display device has been conventionally translucent with backlighting, a reflective display, which uses extraneous light without backlighting, has been developed so as to further lower power consumption.
Moreover, as for a liquid crystal display device, a clear image display has been demanded with higher resolution. Thus, demand has increased for a liquid crystal display device using an active matrix driving method that can provide a clearer image than a conventional direct matrix method.
Lower power consumption has been also demanded on a driving circuit of a liquid crystal display device. A driving circuit with low power consumption has been earnestly studied and developed.
In general, as shown in
FIG. 1
, a liquid crystal display device
1000
using an active matrix driving method includes a liquid crystal driving device
1010
and a liquid crystal panel
1020
. Moreover, the liquid crystal driving device
1010
includes a control circuit
1011
, a data line driving circuit
1012
, and a common electrode voltage generating circuit
1013
. The liquid crystal panel
1020
includes a semiconductor substrate (TFT substrate)
1021
having transparent pixel electrodes and a thin-film transistor (TFT) thereon, an opposing substrate
1022
having a transparent common electrode formed entirely thereon, and liquid crystal filled between the two substrates being opposed to each other.
Data lines and scanning lines are disposed on the semiconductor substrate (TFT substrate)
1021
. The data lines transmit a plurality of level voltages (gradation voltage) to be applied to the pixel electrodes and the scanning lines transmit switching (scanning) control signals to TFT elements. The data lines have a relatively large capacitive load due to a liquid crystal capacity between the opposing substrate electrodes, a capacity appearing on the intersections with the scanning lines, and the like.
The following will discuss a liquid crystal driving device of the liquid crystal display device.
The control circuit
1011
generates a driving control signal, a scan control signal, a common electrode control signal, and so on in response to a signal such as a parallel synchronizing signal and a video signal.
The data line driving circuit
1012
generates a plurality of gradation voltages for driving the data lines in response to a driving control signal.
Moreover, the common electrode voltage generating circuit
1013
supplies a predetermined voltage to the common electrode in response to a common electrode control signal.
A scan control signal controls the TFT, gradation voltage is applied to the pixel electrodes, a transmittance of liquid crystal is varied according to a potential difference between the pixel electrode and the opposing substrate electrode, and an image is displayed.
Gradation voltage is applied to the pixel electrodes via the data lines and is applied to all the pixels connected to the data lines in a single frame period (about {fraction (1/60)} second). Hence, the data line driving circuit needs to rapidly drive the data lines serving as a capacitive load with high voltage accuracy.
As described above, the data line driving circuit
1012
needs to rapidly drive the data lines serving as a capacitive load with high voltage accuracy. Further, when being used for portable equipment, low power consumption is demanded. Therefore, a variety of data line driving circuits have been developed to satisfy the above-mentioned needs (high accuracy, high speed, and low consumption of output voltage).
As a simple driving circuit for outputting a plurality of level voltages in
FIG. 1
, a driving circuit of
FIG. 2
has been known, which is composed of a resistor string (multilevel voltage generating circuit)
200
and decoders
300
each including a switch group
301
.
In
FIG. 2
, as a simple configuration, voltage taken out from a connecting terminal of the resistor string (multilevel voltage generating circuit)
200
is selected in the decoder
300
including the switch group
301
, and the voltage is directly outputted to the data lines of a liquid crystal display panel (e.g.,
1020
in
FIG. 1
) connected to a output terminal group
400
. Besides, a level voltage corresponding to each data line can be selected in the decoder
300
in response to a digital select control signal, which is one of driving control signals.
Power consumption of the driving circuit shown in
FIG. 2
is determined by current applied to the resistor string
200
. If the current is lowered, power consumption can be reduced. However, a driving period (a single output period) of a level voltage to the data line is generally determined by the number of scanning lines of the liquid crystal display panel. In case of a panel having a large number of pixels, a single output period is short and high-speed driving is necessary.
A speed of the driving circuit shown in
FIG. 2
is dependent upon the magnitude of current applied to the resistor string
200
, and charge supplied to the data lines is supplied from the resistor string
200
. Hence, the circuit is large in impedance, and it is necessary to sufficiently increase the current of the resistor string
200
to perform high-speed driving in the driving circuit shown in FIG.
2
. In this case, power consumption increases.
As a driving circuit for solving the above problem, for example, Japanese Patent Laid-Open No. 10-301539 discloses a driving circuit configured as FIG.
3
.
Referring to
FIG. 3
, the driving circuit includes output circuits
900
, which are respectively disposed on the outputs of the driving circuit shown in FIG.
2
. The output circuit
900
has a switch
901
which connects the output of the decoder
300
and an output terminal
400
, an N-channel MOS transistor (NMOS)
902
, and a P-channel MOS transistor (PMOS)
903
. The N-channel MOS transistor (NMOS)
902
has the drain connected to a high-potential side power source VDD, the source connected to the output terminal
400
, and the gate connected to the output of the decoder
300
. The P-channel MOS transistor (PMOS)
903
has the source connected to the output terminal
400
, the drain connected to a lower-potential side power source VSS, and the gate connected to the output of the decoder
300
.
Besides, the switch
901
is controlled by, for example, an operating control signal generated in an operating control signal generating circuit
800
or an operating control signal generated in the control circuit
1011
of FIG.
1
. Namely, when the switch
901
is turned off during a spare charge/discharge period, which is provided in a first half of an output period, a source follower operation of the transistor
902
or
903
achieves faster speed to about a voltage shifted from a selected level voltage by a threshold voltage of the transistor. After the spare charge/discharge period, the switch
901
is turned on, charge is directly supplied from the resistor string
200
to the data lines like the driving circuit shown in
FIG. 2
, and driving is made at a selected level voltage.
In the driving circuit of
FIG. 3
, during the spare charge/discharge period, charge is supplied from the power source, which is connected to the drain of the transistor, to the data lines by impedance conversion in the source follower operation of the transi
Dinh Son T.
McGinn & Gibb PLLC
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