DRAM with bias sensing

Details DRAM with bias sensing DRAM with bias sensing

2001-12-12

2003-08-05

Lam, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S207000, C365S190000

Reexamination Certificate

active

06603693

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to memory devices and in particular the present invention relates to dynamic random access memories (DRAM).
BACKGROUND OF THE INVENTION
Semiconductor memory systems are comprised of two basic elements: memory storage areas and memory control areas. DRAM, for example, includes a memory cell array, which stores information, and peripheral circuitry, which controls the operation of the memory cell array. A DRAM cell is an addressable location that can store one bit (binary digit) of data. In its most common form, a DRAM cell consists of two circuit components: a storage capacitor and an access field effect transistor. The capacitor holds the value of each cell, namely a logic “1” or a “0,” as a charge on the capacitor. Because the charge on a capacitor gradually leaks away, DRAM capacitors must be refreshed on a regular basis. A memory device incorporating a DRAM memory includes logic to refresh (recharge) the capacitors of the cells periodically or the information will be lost. Reading the stored data in a cell and then writing the data back into the cell at a predefined voltage level refreshes a cell. The required refreshing operation is what makes DRAM memory dynamic rather than static.
The transistor of a DRAM cell is a switch to let control circuitry either read the capacitor value or to change its state. The transistor is controlled by a row line coupled to its gate connection. In a read operation, the transistor is activated and sense amplifiers coupled to bit lines (columns) determine the level of charge stored in the memory cell capacitor, and reads the charge out as either a “1” or a “0” depending upon the level of charge in the capacitor. The sense amplifier circuitry typically has balanced pull-up and pull-down circuitry.
The read margin of a DRAM memory cell is defined as the difference between a charge level stored on the memory cell and a sensing level, or threshold, of the sense amplifier. In some designs, it may be desirable to increase the data ‘one’ cell margin. This is typically accomplished by storing more charge on the memory cell or reducing the leakage of the cell. This solution, however, has some drawbacks such as layout, cost and power requirements.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a DRAM in which the memory cell margin can be adjusted.
SUMMARY OF THE INVENTION
The above-mentioned problems with DRAM's and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
In one embodiment, a memory device comprises a plurality of memory cell capacitors, digit lines selectively couplable to the plurality of memory cell capacitors, sense circuitry coupled to the digit lines, and a reference cell coupled to the sense circuitry to force a differential voltage between the digit lines.
A DRAM memory device comprises a plurality of memory cell capacitors, row lines selectively couplable to the plurality of memory cell capacitors, and sense circuitry couplable to first and second digit lines. A reference line contains a charge having a voltage of X, where Vss<X<½ Vcc. The reference line is couplable to the second digit line. Control circuitry is provided to activate one of the row lines and couple the second digit line to the sense amplifier such that the second digit line voltage is reduced below ½ Vcc.
A method of reading a memory cell comprises equilibrating first and second digit lines to a common voltage, accessing the memory cell and coupling the memory cell to the first digit line, and coupling a reference cell to the second digit line. The reference cell decreases a voltage of the second digit line below the common voltage. A differential voltage between the first and second digit lines is then sensed.


REFERENCES:
patent: 4575819 (1986-03-01), Amin
patent: 4855803 (1989-08-01), Azumai et al.
patent: 5053648 (1991-10-01), van den Elshout et al.
patent: 5148391 (1992-09-01), Zagar
patent: 5270241 (1993-12-01), Dennison et al.
patent: 5351213 (1994-09-01), Nakashima
patent: 5388076 (1995-02-01), Ihara
patent: 5418739 (1995-05-01), Takasugi
patent: 5732013 (1998-03-01), Von Basse et al.
patent: 5757690 (1998-05-01), McMahon
patent: 5831892 (1998-11-01), Thewes et al.
patent: 5900008 (1999-05-01), Akao et al.
patent: 5917744 (1999-06-01), Kirihata et al.
patent: 5961653 (1999-10-01), Kalter et al.
patent: 5966315 (1999-10-01), Muller et al.
patent: 5982682 (1999-11-01), Nevill et al.
patent: 5995409 (1999-11-01), Holland
patent: 6097649 (2000-08-01), Chiang et al.
patent: 6128225 (2000-10-01), Campardo et al.
patent: 6134137 (2000-10-01), Kurth et al.
patent: 6154864 (2000-11-01), Merritt
patent: 6243285 (2001-06-01), Kurth et al.

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