DRAM sensing scheme for eliminating bit-line coupling noise

Static information storage and retrieval – Read/write circuit – Precharge

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365149, G11C 700

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active

058703438

ABSTRACT:
A pre-charge and isolation circuit for a folded bit line DRAM array to reduce noise coupling between adjacent bit lines of a DRAM array by connecting only one bit line within one sub-array to be connected to a sense amplifier, while the complementary bit line used for the reference voltage of the sense amplifier is selected from an adjacent sub-array, is disclosed. The isolation pre-charge circuit will be connected to a pair of bit lines within a DRAM array to pre-charge portions the pair of bit lines to a reference voltage level and to connect a selected DRAM cell to a latching sense amplifier.

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M. Aoki et al. "A 60-ns 16mb CMOS DRAM With a Transposed Data-Line Structure" IEEE Trans Sloid-State Circuits SC-23, No. 5, p. 1113, 1998.

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