Static information storage and retrieval – Read/write circuit – Precharge
Reexamination Certificate
2002-10-10
2004-11-16
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Precharge
C365S233100, C365S233500
Reexamination Certificate
active
06819610
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and particularly relates to a semiconductor memory device which performs precharge operations.
2. Description of the Related Art
Certain types of electrical equipment such as cellular phones have conventionally used SRAMs (static random access memories) as memories. SRAMs tend to have a low circuit density, so that an increase in the memory volume will result in a substantial cost increase. DRAMs (dynamic random access memory), on the other hand, are suitable for the implementation of a large memory volume at low costs. In order to take advantage of the past accumulation of SRAM-based configurations, it is desirable to provide a DRAM that is equipped with an interface equivalent to that of an SRAM.
It is necessary to periodically refresh data stored in the DRAM memory cells whereas there is no need for a refresh operation in SRAMs. In order to provide a DRAM acting like an SRAM that has no need for refreshing, refresh operations need to be automatically performed at proper timing in such a manner that can conceal the refresh operations from the exterior of the device.
Pairs of bit lines are precharged to Vcc/2. When a word line is activated at the time of a read operation, pairs of bit lines connected to relevant memory cells produces a potential difference, which is amplified by sense amplifiers for data retrieval. After the passage of a time period preset by internal circuitry, the word line is deactivated, and an auto-precharge is performed to bring the pairs of bit lines to the Vcc/2 level. With this, the read operation comes to an end.
In the SRAM-like DRAMs, bit lines are set to the precharge potential Vcc/2 immediately after a write operation or a read operation, thereby suppressing a leak of electric charge to a minimum level where such leak occurs between memory cells and bit lines. This improves refresh characteristics.
In the SRAM-like DARMs as described above, an auto-precharge is performed at the time of a data read operation, so that the pairs of bit lines of sense amplifiers are automatically set to the Vcc/2 level after the read operation. Because of this, there is a need to newly activate a word line for each data access even when successive accesses are directed to column addresses on the same word line. As a result, high-speed data retrieval such as that of a conventional DRAM page mode cannot be achieved when accesses are directed to the same word line.
Accordingly, there is a need for a DRAM that is provided with an auto-precharge function so as to act like an SRAM, and allows data to be read with a page mode and a burst mode.
SUMMARY OF THE INVENTION
It is a general object of the present invention to provide a semiconductor memory device that substantially obviates one or more of the problems caused by the limitations and disadvantages of the related art.
Features and advantages of the present invention will be set forth in the description which follows, and in part will become apparent from the description and the accompanying drawings, or may be learned by practice of the invention according to the teachings provided in the description. Objects as well as other features and advantages of the present invention will be realized and attained by a semiconductor memory device particularly pointed out in the specification in such full, clear, concise, and exact terms as to enable a person having ordinary skill in the art to practice the invention.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a semiconductor memory device including a first bit line connected to a memory cell via a transistor, a transfer gate, a second bit line connected to the first bit line via the transfer gate, a sense amplifier connected to the second bit line, a first precharge circuit for precharging the first bit line, a second precharge circuit for precharging the second bit line, a control circuit which precharges the first bit line by the first precharge circuit after closing the transfer gate, followed by subsequent precharging of the second bit line by the second precharge circuit.
In the semiconductor memory device as described above, the first precharge circuit for precharging the first bit lines of the memory cell portion and the second precharge circuit for precharging the second bit lines of a sense amplifier portion are provided separately. With this provision, the bit lines of the sense amplifier portion can be precharged by the second precharge circuit after the bit lines of the memory cell portion are precharged by the first precharge circuit with the transfer gate having been closed. During the time period preceding the precharging of the bit lines of the sense amplifier portion, the sense amplifiers still maintain their data stored therein, so that the data can be successively read from different column addresses on the same row address with a page mode operation or a burst mode operation.
Further, when the bit lines of the sense amplifier portion are to be precharged, the bit lines of the memory cell portion having a large parasitic capacitance have been already auto-precharged, so that only the bit lines of the sense amplifier portion need to be precharged by deactivating the sense amplifiers. It is thus possible to carry out a high-speed precharge operation and promptly switch to a next read or write operation.
Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.
REFERENCES:
patent: 5091889 (1992-02-01), Hamano et al.
patent: 5339274 (1994-08-01), Dhong et al.
patent: 6442088 (2002-08-01), Tsuchida et al.
Eto Satoshi
Matsumiya Masato
Miyo Toshiya
Nakamura Toshikazu
Sato Ayako
Arent & Fox PLLC
Dinh Son T.
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