DRAM having exclusively enabled column buffer blocks

Details DRAM having exclusively enabled column buffer blocks DRAM having exclusively enabled column buffer blocks

1992-03-13

1994-07-12

Dixon, Joseph L.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

36523003, G11C 800

Patent

active

053294890

ABSTRACT:
A random access array memory device which uses a static buffer as a cache for speeding the access times achievable for data retrieval from the device. The static buffer is operationally divided into two or more blocks so that each block holds a block of data from a different row of the array. The division of a single buffer into several operational blocks significantly increases the "hit" probability of the cache, allowing fast access from the buffer. A control system stores the row address (TAG) of each of the multiple blocks and compares that address to the row address of the data desired and signals the result of that comparison. Random access memory arrays of the multiple line cache configuration are employed in data processing systems including a CPU, address and data buses, control logic, and multiplexers.

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Ward, S. and Zak, R., "Static-column RAM as Virtual Cache", Laboratory for Computer Science, MIT, Cambridge, Mass.

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