DRAM cell arrangement

Details DRAM cell arrangement DRAM cell arrangement

2001-07-03

2002-12-10

Meier, Stephen D. (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S239000, C438S386000, C438S399000, C257S296000, C257S305000

Reexamination Certificate

active

06492221

ABSTRACT:

The invention relates to a DRAM cell arrangement and a method for fabricating it.
BACKGROUND
Generally endeavors are made to produce a DRAM cell arrangement with an ever higher packing density. For a DRAM cell arrangement in which the information is stored in the form of a charge on a storage capacitor, the problem arises of producing the storage capacitor on a small area but nonetheless providing it with a sufficiently high capacitance in order that the signal of the charge is not submerged in background noise when the information is read out.
K. Hoffmann, “VLSI-Entwurf: Modelle und Schaltungen [VLSI Design: Models and Circuits]” (1996), pages 411 to 415 describes a DRAM cell arrangement having so-called folded bit lines. On account of comparable bulk resistances and coupling capacitances, the background noise of bit lines which are arranged close together is similar. In a DRAM cell arrangement having folded bit lines, the signal of a bit line which is connected to a storage capacitor to be read is compared with a signal of an adjacent bit line, which only comprises the background noise. Since the two bit lines are adjacent to one another, part of the background noise can thus be filtered out. Consequently, such a differential reading method makes it possible to read out a smaller charge, which produces a smaller voltage change on the bit line. A minimum capacitance of the storage capacitor required for reading out the information is smaller than in the case of a DRAM cell arrangement having so-called open bit lines, i.e. without folded bit lines. A word line which addresses the memory cell to be read must not be connected to any memory cell connected to the adjacent bit line, in order that the signal of the adjacent bit line only comprises background noise. In the case of the DRAM cell arrangement described, a memory cell comprises a transistor and a storage capacitor, which are arranged next to one another. A first word line and a second word line are arranged above the memory cell. Mutually adjacent memory cells along the word lines are alternately connected to the first word line and the second word line. To that end, the transistors and the storage capacitors of the memory cells are arranged in such a way that a transistor and a storage capacitor of different memory cells are alternately arranged next to one another along the word lines. The bit lines run transversely with respect to the word lines.
T. Ozaki et al., “0.228 &mgr;m
2
Trench Cell Technologies with Bottle-Shaped Capacitor for 1 Giga-Bit DRAMs,” IEDM (1995) 661, describes a DRAM cell arrangement having open bit lines. A memory cell comprises a planar transistor and a storage capacitor connected in series therewith. Two planar transistors having a common source/drain region are arranged between two respective storage capacitors whose storage nodes are arranged in depressions in a substrate. In order to increase the capacitance of the storage capacitor, firstly an upper region of the depression is produced, the sidewalls of which region are provided with an oxide. Afterward, the oxide is removed at the bottom of the depression and the depression is deepened further, thereby producing a lower region of the depression. The lower region of the depression is widened by a wet etching process, with the result that a cross section of the lower region of the depression is larger than a cross section of the upper region. By virtue of the widening of the lower region of the depression, the surface area of a capacitor dielectric which covers areas of the depression is enlarged, and the capacitance of the storage capacitor is thus increased.
EP 0 852 396 describes a DRAM cell arrangement in which, in order to increase the packing density, a transistor of a memory cell is arranged above a storage capacitor of the memory cell. Active regions of the memory cells are in each case surrounded by an insulating structure arranged in a substrate. A depression is produced in the substrate for each memory cell, a storage node of the storage capacitor being arranged in the lower region of the depression and a gate electrode of the transistor being arranged in the upper region of the depression. An upper source/drain region, a channel region and a lower source/drain region of the transistor are arranged one above the other in the substrate. The lower source/drain region is connected to the storage node at a first sidewall of the depression. The insulating structure adjoins a second sidewall, opposite to the first sidewall, of the depression, with the result that the storage node does not adjoin the substrate there. A capacitor electrode of the storage capacitor is formed by the ad diffusion of dopant into the substrate. As in the publication by T. Ozaki et al. (see above), a lower region of the depression is widened in this case, too. A bit line adjoins the upper source/drain region and runs above the substrate. The gate electrode is insulated from the substrate and from the bit lines by a gate dielectric and the insulating structure. The gate electrode adjoins a word line running above the bit line.
SUMMARY
The invention is based on the problem of specifying a DRAM cell arrangement which has folded bit lines, whose word lines and bit lines can be produced with high electrical conductivity and which can, at the same time, be fabricated with a high packing density. Furthermore, the intention is to specify a method for fabricating it.
The problem is solved by means of a DRAM cell arrangement in which memory cells are arranged in columns which run parallel to a y-axis and rows which run parallel to an x-axis, in a substrate. The memory cells of a column are connected to a bit line which runs above a main area of the substrate. The memory cells of a row are alternately connected to a first word line and a second word line. Furthermore the memory cells each comprise a pillar-shaped connection structure. First parts of the first word line are each arranged offset in the y-direction, i.e. in the positive direction along the y-axis, with respect to one of the connection structures of the memory cells to which the first word line is connected, with the result that this connection structure is overlapped from above but not covered. A second part of the first word line is strip-shaped, runs above the main area and essentially parallel to the x-axis and adjoins the first parts of the first word line from above. Sidewalls of the first word line are provided with insulating spacers. First parts of the second word line are arranged between the spacers of mutually adjacent first word lines of the memory cells. The first parts of the second word line are each arranged offset oppositely to the y-direction, i.e. in the negative direction along the y-axis, with respect to one of the connection structures of the memory cells to which the second word line is connected, with the result that this connection structure is overlapped from above but not covered. A second part of the second word line is strip-shaped, runs above the main area and essentially parallel to the x-axis, adjoins the first parts of the second word line from above and is arranged above the first word line and the bit line. The first word line and the second word line overlap the row.
The problem is furthermore solved by means of a method for fabricating a DRAM cell arrangement, in which memory cells are produced in columns which run parallel to a y-axis and rows which run parallel to an x-axis. A pillar-shaped connection structure is in each case produced for the memory cells. Bit lines are produced which are respectively connected to the memory cells of a column. A first insulating layer is applied over the connection structures of memory cells. First contact holes are produced in the first insulating layer, which uncover parts of each second connection structure of the memory cells of a row in such a way that the first contact holes are arranged offset in the y-direction with respect to the connection structures. Conductive material is deposited, with the result that the firs

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