DRAM cell

Details DRAM cell DRAM cell

2005-02-15

2005-02-15

Tsai, H. Jey (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S396000

Reexamination Certificate

active

06855597

ABSTRACT:
A method of manufacturing a DRAM cell includes forming an isolation layer on a given region of a substrate to define an active region having a plurality of line shaped sub-regions; forming at least a pair of cell transistors in each line shaped sub-region, each cell transistor of a pair having a common drain region and respective source regions; forming a bit line pad on each common drain region and a storage node pad on each source region; forming a bit line pad protecting layer pattern having portions parallel to the word line, that covers the bit line pad; and forming storage nodes on storage node pads. The storage nodes of the DRAM cell contact with the storage node pads and are insulated electrically from the bit line pad by the bit pad protecting layer pattern.

REFERENCES:
patent: 5436187 (1995-07-01), Tanigawa
patent: 6403416 (2002-06-01), Huang et al.
patent: 6403996 (2002-06-01), Lee
patent: 6417097 (2002-07-01), Hwang et al.
patent: 6483136 (2002-11-01), Yoshida et al.
patent: 2001036044 (2001-02-01), None

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