Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-01-27
2001-03-27
Clark, Sheila V. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S391000, C257S336000, C257S344000, C257S324000, C257S192000, C257S194000
Reexamination Certificate
active
06207999
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor devices, specifically to semiconductor memories and more specifically to a structure of mask read only memories for minimizing band-to-band leakage.
BACKGROUND
Memory devices are driven by new applications and requirements of the future. Advance in the fields of computer and communications will demand large quantities of various species of memories. For example, computer interfaces will hopefully be operated by speech processing or visual processing. Great capacity and processing speed are required for such audio and video signal processing. Besides, other kinds of communication applications and interfaces also require a lot of memory. Memory technology will continue to move in the direction of increased numbers of devices in a wafer.
Read only memory (ROM) are devices which include ROM cells for coding data and a periphery controlling devices to control the operation of the cells. In read only memories, each bit of data is stored in a cell, like a single n-channel transistor or ROM cell. As is well known in the art, the programming of the ROM is executed by controlling a threshold voltage of the MOS transistor by the implantation of dopant to construct the memory cell with the desired coding status.
In general, the mask ROM includes different types of devices with different threshold voltages. A type of device is formed in one active area and another type of device with a threshold voltage mask is formed in another active area during the process. In MOS transistors for mask ROM, the threshold voltages of the channel regions under the gates are set to the same value before data writing. Thereafter, ions are selectively implanted into determined regions to change the threshold voltages thereof for data writing. One of the methods for adjusting the threshold voltage is achieved by ion implantation to some of the transistor gates. This method raises the threshold voltage of the n-channel device by doping boron with a heavy dose. The prior arts relating to the ROM can be seen in U.S. Pat. No. 5,372,961 and U.S. Pat. No. 5,538,906 disclosed by Noda and Aoki, respectively. The process of ion implantation having high dose boron through the sacrifice oxide or the polysilicon gate into the substrate is widely used to fabricate the normally off mask ROM devices.
However, the high dose boron implantation results in a lower junction breakdown voltage of the coded MOS and also a very high leakage current between the adjacent bit lines. As mentioned in a U.S. Pat. No. 5,597,753 disclosed by Sheu, the high leakage current results in very high standby current. Another problem occurs with the ROM code implantation. As what is well-known in the art, after the coding implantation is carried out, a thermal process is used to activate the implanted dopants. The process can cause counter doping of the adjacent bit lines, thereby increasing the bit line resistance and substantially degrading the performance of the ROM devices. One prior art method to reduce the bit line resistance is disclosed by Hong in U.S. Pat. No. 5,571,739.
SUMMARY
The object of the present invention is to provide a mask ROM memory to minimize the band-to-band leakage. The substrate includes a normal NMOS device region and a NMOS cell region for coding. An isolation region is formed between the normal NMOS device region and the NMOS cell region. A gate oxide layer is formed on the normal NMOS device region and a coding oxide layer is formed on the NMOS cell region, respectively. In the preferred embodiments, the coding oxide layer has a thickness of about two to ten times of that of the gate oxide layer. Main gates are respectively formed on the gate oxide layer and the coding oxide layer. In the present invention, the main gates comprise materials like metal and metal compounds. Spacers are formed on the side walls of the main gates. First doped regions of source and drain regions, or namely lightly doped drains (LDD) and sources, are formed under the spacers and adjacent to the main gates. Second doped regions of the source and drain regions are formed next to and outside the first doped regions. The second doped regions have a heavier dose than the first doped regions. A p type doped region is formed under the coding oxide layer and in adjacent to a surface of the NMOS cell region. The p type doped region is doped with dopants like aluminum-containing, gallium-containing, indium-containing, or thallium-containing dopants. The p type doped region has higher resistance than the other normal NMOS devices during the operation. In addition, the mask ROM can further includes a polysilicon layer formed between the gate oxide layer and at least one of the main gates on the NMOS device region.
REFERENCES:
patent: 5081052 (1992-01-01), Kobayashi et al.
patent: 5200802 (1993-04-01), Miller
patent: 5397908 (1995-03-01), Dennison et al.
patent: 5536962 (1996-07-01), Pfiester
patent: 5793086 (1998-08-01), Ghio et al.
patent: 6037615 (2000-03-01), Matsuyama et al.
Clark Sheila V.
Fenty Jesse A.
Harness & Dickey & Pierce P.L.C.
Texas Instruments--Acer Incorporated
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