Digital self-calibration scheme for a pipelined A/D converter

Details Digital self-calibration scheme for a pipelined A/D converter Digital self-calibration scheme for a pipelined A/D converter

2000-10-18

2001-05-15

Wamsley, Patrick (Department: 2819)

Coded data generation or conversion

Converter calibration or testing

C341S118000

Reexamination Certificate

active

06232898

ABSTRACT:

BACKGROUND AND SUMMARY OF THE INVENTION
The present invention relates to digital self-calibration schemes for pipelined A/D converters.
Background: Analog to Digital Conversion
Analog to digital conversion is the process of converting an analog data signal, which is most commonly represented as voltage, into a digital format. Determining a digital value which represents a particular analog input is known as “quantization”. Serial, delta-sigma or oversampling, parallel, and pipelined are some of the many different analog to digital conversion architectures which exist. Different architectures are suited to different needs.
Serial analog to digital architecture offers the widest range of performance in analog to digital conversion, from low power and low resolution to quantizations with very high resolutions. Serial architecture quantizes analog data at the rate of one bit per cycle. Therefore, a digital sample having N bits of resolution will take N cycles to fully quantize. Delta-sigma analog to digital architecture is used in audio signal processing. The architecture is designed to translate high-speed, low-resolution samples into higher-resolution, lower-speed output. This process is also referred to as oversampling because more samples of the analog data are quantized than actually become output. Parallel analog to digital architecture provides the fastest quantization rate per analog signal. In the parallel architecture, a digital value per cycle is produced for each analog data sample, without regard to N, the number of bits of resolution. Parallel architecture requires that all quantization levels be simultaneously compared to the analog signal. This results in the use of 2N−1 comparators and 2N+1 resistors to achieve a digital value, with N bits of resolution, per cycle.
Background: Pipelined Analog to Digital Architecture
Pipelined analog to digital architecture, like serial analog to digital architecture, is a method of quantizing an analog signal in stages. Algorithms exist for obtaining either 1 or 1.5 bits of resolution per stage. In a 1.5-bit per stage converter, the digital output of each stage is either 1, 0, or −1. In a 1-bit per stage converter, the digital output of each stage is either 1 or −1. For either algorithm, N stages are required for an N-bit digital value. One bit is resolved at each stage with the result and analog signal sample passed along to the next stage for resolution of another bit. Producing a single digital value for a single analog input requires N cycles, one for each stage. However, the pipelining permits a high degree of parallelism, so that one output per cycle can be produced after the pipeline fills up.
Pipelined analog to digital converters have many applications. They are particularly useful when low voltage, high speed, high resolution quantization is required. The pipelined analog to digital conversion architecture's ability to meet these demands makes it ideal for high volume telecommunications application such as various digital subscriber lines, digital signal processing at video rates, and for stand alone high speed analog to digital converters.
The advantage of pipelined analog to digital conversion is that each stage of resolution is separated. Once the analog signal is resolved at the first stage and the result passed to the second stage, a new signal can be processed by the first stage. The passing of result and signal from stage to stage continues to stage N at which point a digital value of N bits of resolution can be produced. Quantization of the first signal to N bits of resolution is achieved in N cycles. However, because each stage resolves one bit and passes the result to the next stage, the former stage is free to resolve a bit of the next analog sample.
This staged design allows N analog samples to be in the process of quantization simultaneously. Once the first analog sample is quantized, after N cycles, each successive analog sample is quantized one cycle later. Thus, there is only one cycle delay per digitized signal after the first is fully quantized. Pipelined analog to digital conversion therefore results in the fastest throughput rate of any analog to digital conversion that quantizes one-bit per conversion cycle, as it is capable, after an N−1 cycles start up period, of quantizing one sample per cycle.
Background: Analog to Digital Conversion Error
Errors can be introduced into the conversion process at different stages and by different components. Two of the most common components in analog to digital conversion which can cause error are capacitors and amplifiers. Capacitors can introduce error because of a mismatch concerning the capacitance ratio of two capacitors or due to a capacitor's non-linearity over a given voltage range. Amplifiers can introduce error by way of gain error, that is, a fixed difference of output versus input. Amplifiers can also introduce error through non-linearity. Non-linearity is characterized by a change in the amplifier's gain as the output gets higher. Non-linearity can be depicted graphically as the deviation from a straight line from the plot of output versus input.
Background: Capacitor Mismatch and Non-linearity
A digital self-calibration technique for pipelined analog to digital converters which corrects for capacitor mismatch has been disclosed in Hae-Seung Lee, A 12-B 600 KS/S DIGITALLY SELF-CALIBRATED PIPELINED ALGORITHMIC ADC, IEEE Journal of Solid State Circuits, Vol 29, No. 4, April 1994, at 509, which is incorporated herein by reference. This article demonstrates the necessary steps for determining the mismatch ratio of two nominally equal capacitors. The difference of the capacitance between two nominally equal capacitors, C
1
and C
2
, can be represented as C
1
=(1+&agr;
i
)C
2
where &agr;
i
represents the mismatch ratio in capacitance between capacitors C
1
and C
2
. Once &agr;
i
is known, the error due to capacitance mismatch can be canceled by adding a digital correction quantity:
α
i
2
i
[
(
D
⁢
(
i
)
/
2
i
-
D
⁢
(
i
+
1
)
/
2
i
+
1
-
D
⁢
(
i
+
2
)
/
2
i
+
2
-
…
⁢
 
]
to the digital output, where D(i) represents the digital output of the ith stage of a pipelined analog to digital converter.
In the Lee article, several assumptions are made concerning the need for digital self-calibration and the extent to which error should be corrected. The article assumed that the only linearity error present in a 1.5 bits per stage converter is caused by capacitor mismatch. This assumption was based on the presence of an operational amplifier at each stage of the pipeline with “high enough” gain to effectively eliminate the amplifier gain and non-linearity. In other words, the article assumes an amplifier with infinite gain. However, such an amplifier is merely theoretical. Further, an amplifier with a “high enough” gain is costly to produce (especially in low voltage designs) in terms of monetary cost, power consumption and area requirement. Requiring such an operational amplifier for each stage of the pipeline would increase the cost of the converter significantly. Further, higher bit resolutions will require amplifiers with higher gain. Higher gain creates a larger output swing which can cause slew rate and phase margin degradation.
Background: Amplifier Gain and Non-linearity
If the gain error of an amplifier is fixed, it can then be corrected in a fashion similar to the capacitor error correction technique described by Lee. This would require designing an amplifier with constant gain over its entire input signal range. This would allow an error correction constant to be applied to the digital output of the pipelined analog to digital converter to correct for amplifier gain errors. However, such an amplifier design is difficult and costly to implement. For example, an amplifier with a 60 dB raw gain would have to have a constant gain within 10% across the entire signal range in order for a single amplifier gain correction constant to be used with a 14-bit analog to digital

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