Doped spacer liner for improved transistor performance

Details Doped spacer liner for improved transistor performance Doped spacer liner for improved transistor performance

2002-03-26

2003-06-24

Whitehead, Jr., Carl (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S301000, C438S305000, C438S306000, C438S307000, C438S230000, C438S231000, C438S783000, C438S787000

Reexamination Certificate

active

06583016

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a semiconductor device having improved transistor performance and enabling methodology. The present invention has particular applicability in fabricating high density semiconductor devices with high speed integrated circuits having submicron design features and shallow junction depths.
BACKGROUND ART
The escalating demand for high density and performance impose severe requirements on semiconductor fabrication technology, particularly for enhanced transistor performance and high operating speed. Transistor performance depends upon various factors and can easily be degraded by various processing operations during fabrication, such as plasma deposition techniques wherein the substrate is exposed to high temperatures and plasmas, as during plasma enhanced chemical vapor deposition. The need for high operating speed also requires the use of dielectric materials having a relatively low dielectric constant, such as about 3.9 or less. The value of a dielectric constant (k) expressed herein is based upon the value of 1 for a vacuum.
In implementing conventional fabrication techniques, as illustrated in
FIG. 1
, a gate electrode
11
is typically formed over a semiconductor substrate
10
with a gate dielectric layer
12
, e.g., gate oxide layer, therebetween. Ion implantation is then conducted to implant shallow source/drain extensions
13
. An oxide liner
14
is then formed on side surfaces of gate electrode
11
and the upper surface of substrate
10
, as at a thickness of about 50 Å to about 200 Å to protect the substrate surface during subsequent etching to form sidewall spacers
15
, typically formed of silicon nitride. Reference character
14
illustrates a moderate or heavy doped source/drain region typically implanted subsequent to forming sidewall spacers
16
.
Difficulties are encountered in implemented conventional semiconductor fabrication techniques, such as those used to form the structure illustrated in FIG.
1
. For example, during high temperature processing, as during deposition of the silicon oxide liner
14
, by low pressure chemical vapor deposition, typically at a temperature of about 700° C. or higher, dopant impurities implanted into the source/drain extensions
13
, such as P-type impurities, e.g., boron (B) and boron difluoride (BF
2
) impurities, diffuse and segregate in the oxide liner
14
. A lower-temperature 400° C. CVD liner oxide can be used to prevent such out diffusion and dopant loss. However, dopant loss occurs during high temperature activation appealing, as at a temperature greater than 1000° C. for 5 to 10 seconds. Such diffusion loss from the source/drain extensions are manifestly. disadvantageous, as by increasing the resistance of the source/drain extensions. A prior attempt to resolve this problem comprises ion implanting the dopant impurity, e.g., B or BF
2
, at a higher implantation dosage than necessary in order to compensate for dopant diffusion loss. However, this approach disadvantageously results in a deeper junction depth (X
j
), which is inconsistent with the continuous drive toward miniaturization.
DISCLOSURE OF THE INVENTION
An advantage of the present invention is a method of fabricating a high density semiconductor device having transistors with improved performance.
Additional advantages and other features of the present invention will be set forth in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to an aspect the present invention, the foregoing and other advantages are achieved in part by a method of manufacturing a semiconductor device, the method comprising: forming a gate electrode, having side surfaces, over an upper surface of a substrate with a gate dielectric layer therebetween; ion-implanting a dopant into the substrate, using the gate electrode as a mask; to form shallow source/drain extensions; forming an oxide liner on the side surfaces of the gate electrode and upper surface of the substrate; and ion-implanting the dopant into the oxide liner.
Embodiments of the present invention include ion-implanting B or BF
2
into the substrate to form shallow source/drain extensions having a first impurity concentration, depositing a conformal oxide liner on the upper surface and side surfaces of the gate electrode and on the upper surface of the substrate, ion-implanting B or BF
2
into the oxide liner at the substantially same impurity concentration as in the source/drain extensions, e.g., about 1×10
20
to about 6×10
20
atoms/cm
3
, depositing a spacer layer, such as silicon nitride or silicon oxynitride, and etching to form sidewall spacers. The portion of the silicon oxide liner on the upper surface of the gate electrode may then be removed. Ion-implantation is conducted to form the deep moderate or heavy doped source/drain regions, either before or subsequent to removing the portion of the oxide liner from the upper surface of the gate electrode. Activation annealing may then be conducted.
Additional advantages and aspects of the present invention will become readily apparent to those skilled in the art from the following detailed description, wherein only the preferred embodiment of the present invention is shown and described, simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be realized, the present invention is capable of other and different embodiments, and its several details are capable of modification in various obvious respects, all without departing from the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.


REFERENCES:
patent: 6156598 (2000-12-01), Zhou et al.
patent: 6190982 (2001-02-01), Tseng et al.
patent: 6235600 (2001-05-01), Chiang et al.
patent: 6346468 (2002-02-01), Pradeep et al.

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