Disposable spacer technology for reduced cost CMOS processing

Details Disposable spacer technology for reduced cost CMOS processing Disposable spacer technology for reduced cost CMOS processing

1999-06-24

2003-10-14

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S231000, C438S696000

Reexamination Certificate

active

06632718

ABSTRACT:

FIELD OF THE INVENTION
The invention is generally related to the field of CMOS transistor fabrication and more specifically to forming CMOS transistors using disposable spacers.
BACKGROUND OF THE INVENTION
To remain competitive in today's semiconductor market, companies are under constant pressure to reduce the manufacturing costs. One means of significantly reducing this cost is by eliminating mask levels. Each mask level incorporates a number of steps such as resist coating, exposure, development, alignment check and then several clean-up steps (resist ash, resist strip, megasonic clean). Each mask eliminated can result in considerable reduction in manufacturing cost and improve profit margin.
There are many masking levels in conventional CMOS transistor formation. After several masking levels for the formation of isolation regions and threshold adjust implants, the gate dielectric and polysilicon gate material are deposited. One or more masking levels may then be used to separately dope the NMOS and/or PMOS polysilicon regions. Then the polysilicon is patterned and etched using a gate pattern masking level. Then, there are MDD/LDD PMOS and NMOS masking levels for masking the p-type and n-type MDD/LDD implants from each other. Then, sidewall spacer are formed. This is followed by the NMOS source/drain implant using a mask to block implant from the PMOS regions and a PMOS source/drain implant using another mask to block the implant from the NMOS regions. Subsequent to the formation of the transistor are several masking levels for each layer of interconnect such as masking levels for contact/via etch and metal interconnect etches.
There has been some reduction in the number of mask levels needed. For example, the p-type source/drain and MDD/LDD implants have been optimized in some processes to eliminate the need for a separate p-type polysilicon implant and corresponding mask. However, there is a need to further minimize the number of masking levels in order to reduce manufacturing cost.
SUMMARY OF THE INVENTION
The invention is a method of fabricating a CMOS transistor using a silicon germanium disposable spacer for the source/drain implant. After gate etch, silicon germanium disposable spacers are formed. A NMOS resist pattern is formed exposing the NMOS regions and the n-type source/drain implant is performed. The disposable spacers in the NMOS regions, are removed and, with the NMOS resist mask still in place, the LDD/MDD implant is performed. The process may then be repeated for the PMOS regions.
An advantage of the invention is the elimination of separate masks for the LDD/MDD and source/drain implants.


REFERENCES:
patent: 5200352 (1993-04-01), Pfiester
patent: 5324683 (1994-06-01), Fitch et al.
patent: 5506161 (1996-04-01), Orlowski et al.
patent: 5543339 (1996-08-01), Roht et al.
patent: 6022782 (2000-02-01), Smith et al.
patent: 6087239 (2000-07-01), Juengling
patent: 6127234 (2000-10-01), Gardner et al.
patent: 6159815 (2000-12-01), Lustig et al.
patent: 6221709 (2001-04-01), Sagarwala et al.
patent: 6300207 (2001-10-01), Ju

Affiliated with

Also associated with

Rating

Disposable spacer technology for reduced cost CMOS processing does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Disposable spacer technology for reduced cost CMOS processing, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Disposable spacer technology for reduced cost CMOS processing will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3117565