Direct determination of interface traps in MOS devices

Details Direct determination of interface traps in MOS devices Direct determination of interface traps in MOS devices

2002-06-04

2004-06-08

Pert, Evan (Department: 2829)

Semiconductor device manufacturing: process

With measuring or testing

Electrical characteristic sensed

Reexamination Certificate

active

06746883

ABSTRACT:

BACKGROUND OF INVENTION
1. Field of the Invention
The present invention relates to semiconductor wafer testing. More particularly, this invention relates to characterization of semiconductor/oxide interface traps.
2. Description of the Prior Art
Recently, semiconductor devices have been integrated so highly that integrated semiconductor devices have been designed on a nanometer level instead of a micron level (e.g., The National Technology Roadmap for Semiconductors Technology Needs, SIA, 2001 edition). In accordance with the SIA roadmap, by 2002, scaling of a sub-100 nm device will need a gate oxide thickness (t
ox
) in the range of about 12 to 15 angstroms. However, this raises a thorny problem of how to evaluate quality of an ultra-thin gate oxide layer with a thickness of 10 to 20 angstroms in terms of interface traps (N
it
).
As known by those skilled in the art, two pronounced effects are observed during testing of a MOS device as a gate oxide thickness shrinks down to 30 Å and below, namely, Direct Tunneling Gate Leakage (DTGL) effect and the so-called quantum mechanical effect. These effects render the device characterization more difficult.
A conventional approach to determining the interface traps in a gate oxide interface of a CMOS device is a Capacitance-Voltage (CV) method, which is proposed by Lewis M. Terman in 1962 (Solid-State Electronics, Vol.5(5), p.285-299, Lewis M. Terman, 1962). Unfortunately, the prior art CV method is not able to extract accurate interface traps when the above-mentioned DTGL effect exists. Obviously, the prior art CV method is not an effective approach to the oxide quality evaluation of an ultra-thin gate oxide device. Plus, the prior art CV method requires a large area capacitor structure such that it can not be applied to the measurement of real small MOS devices (with short channel length and narrow width).
Another prior art approach is a so-called Charge-Pumping (CP) method, which is disclosed in articles such as IEEE T-ED, Vol.36, p.1318-1335, P. Heremans et al., 1989; Proc. SSDM, p.841-843, S. S. Chung et al., 1993; IEEE T-ED, Vol.45, No.2, p.512-519, C. Chen et al., 1999; IEEE T-ED, Vol.46, p.1371-1377, S. S. Chung et al., 1999; and IEEE EDL, Vol.20, No.2, p.92-94, P. Masson et al., 1999. However, none of the prior art CP approaches generate an accurate and satisfactory result, in particular when the thickness of a tested gate oxide is less than 12 angstroms and beyond. Consequently, there is a strong need to provide an accurate approach to the measurement of N
it
in the ultra-thin gate oxide age.
SUMMARY OF INVENTION
Accordingly, it is the primary objective of the claimed invention to provide an improved method for accurately characterizing semiconductor/oxide interface traps.
In accordance with the claimed invention, a method for determining interface traps in a semiconductor/oxide interface of a MOS transistor comprising a bulk substrate, a source, a drain, a gate, and a silicon oxide layer beneath the gate is provided. The method includes grounding the bulk substrate, source, and drain, applying a first gate pulse with a fixed low-level gate voltage (V
gl
) and an increasing high-level gate voltage (V
gh
) at a high gate pulse frequency on the gate so as to obtain a first charge-pumping current (I
CP
)−V
gh
curve, applying a second gate pulse having same low-level gate voltage (V
gl
) and same increasing high-level gate voltage (V
gh
) as the first gate pulse at a lower gate pulse frequency on the gate so as to obtain a second I
CP
−V
gh
curve, and subtracting the second I
CP
−V
gh
curve from the first I
CP
−V
gh
curve.
These and other objectives of the claimed invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment, which is illustrated in the various figures and drawings.


REFERENCES:
S.S. Chung et al., “A Novel and Direct Determination of the Interface Traps in Sub-100nm CMOS Devices with Direct Tunnelin Regime (12~16A) Gate Oxide,” 2002 Symposium On VLSI Technology Digest of Technical Papers, pp. 74-75.*
Lewis M. Terman, Solid-State Electronic, vol. 5(5), 1962, p. 285-299.
P. Heremans et al., IEEE T-ed, vol. 36, 1989, p. 1318-1335.
S.S. Chung et al., Proc SSDM, 1993, p. 841-843.
C. Chen et al., IEEE T-ed, vol. 45, No. 2, 1999.
S.S. Chung et al., IEEE T-ed, vol. 46, 1999, p. 1371-1377.
P. Masson et al., IEEE Ed1, vol. 20, No. 2, 1999, p. 92-94.

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