Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-05-16
2004-06-29
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06757875
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to an apparatus for evaluating layer matching deviation in a step of fabricating a semiconductor device.
In fabricating a semiconductor device (hereafter, abbreviated simply as semiconductor fabrication), first, a pattern of a semiconductor is designed and the pattern is stored as CAD data. Based thereon, a photomask is fabricated and the semiconductor element is not fabricated respectively as a single member thereof but a number of devices are simultaneously fabricated on one semiconductor wafer. Therefore, the photomask is drawn with patterns of a number the same as that of devices fabricated on the one semiconductor wafer. However, when the wafer is printed by the mask simply aligned with the same images, the identical circuit pattern is not photographed at a central portion and a peripheral portion of the wafer. This is because warp is necessarily accompanied by the influence of aberration or like errors of an optical system. Therefore, according to a circuit pattern, there is designed a pattern having a margin anticipating a safety factor in consideration of the aberration of the optical system actually used in transcription such that the circuit becomes normal throughout the transcribed wafer. The transcription of the pattern is executed not only for a single layer, but a plurality of overlapped layers in a thickness direction of the wafer. Further, patterns of different layers are formed by being transcribed by different masks and a circuit is constituted for an individual device and therefore, there is needed a connection among the patterns of the different layers. Therefore, shapes of the patterns among the different masks and positional relationship thereof constitutes an important yield factor in fabricating the semiconductor device. Further, as described above, a number of the devices are formed on the wafer and it is necessary that the shapes of the respective patterns and the positional relationship thereamong, are converged in an allowable range (within margin) of the design standard both at the central portion and the peripheral portion. Particularly, since the large amount of semiconductors are fabricated based on the mask and therefore, finishing accuracy thereof is an important item directly influencing on the yield of the product.
Conventionally, control of the yield dependent upon the shape of the wafer pattern in a step of fabricating a semiconductor device is carried out by using SEM (scanning electron microscope) for length measurement. According to the method, at each step of fabricating steps, the pattern shape is measured by SEM and the shape of the pattern is checked to thereby control the yield. According to the method, the pattern shape can be checked at respective steps, however, matching of a pattern formed at a step thereafter cannot be evaluated and therefore, in this regard, it is the current state that the matching is carried out in synthetic evaluation including pattern failure over steps by electric measurement or the like after finishing a final step. According to evaluation executed after finishing the final step, it is difficult to specify at which portion of which step the failed portion is caused and therefore, there is brought about a situation in which enormous time and labor is taken in a necessary modifying operation.
SUMMARY OF THE INVENTION
The present invention relates to an apparatus for evaluating a layer matching deviation which is capable of determining whether a pattern of a semiconductor device fails in an allowable range of design including a relative positional relationship with a pattern of a later step to be able to carry out instruction to improve yield at an early of stage fabricating a semiconductor device.
An apparatus for evaluating a layer matching deviation based on CAD information of the present invention is provided with means for storing CAD data and a function of displaying an overlapped image of a scanning microscope image of a pattern of a semiconductor device formed on a wafer and a CAD image used to fabricate the device read from the storing means and a function of evaluating acceptability of formation of the pattern by displaying an overlapped image of a pattern image of the semiconductor device formed on the wafer and the CAD image of the pattern, and, in addition thereto, is capable of evaluating acceptability of formation of the pattern also with regard to a shape and positional relationship with a pattern to be formed at a later step by displaying an overlapped image of a CAD image of the pattern to be formed at the later step.
REFERENCES:
patent: 5530372 (1996-06-01), Lee et al.
patent: 6078738 (2000-06-01), Garza et al.
patent: 6128403 (2000-10-01), Ozaki
patent: 6493867 (2002-12-01), Mei et al.
patent: 6562638 (2003-05-01), Balasinski et al.
Adams & Wilks
Bowers Brandon
Seiko Instruments Inc.
Siek Vuthe
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