Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses – Using delay
Reexamination Certificate
2005-08-23
2005-08-23
Butler, Dennis M. (Department: 2115)
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
Using delay
C713S503000
Reexamination Certificate
active
06934867
ABSTRACT:
A method of calibrating an interface is provided to automatically achieve a minimal cycle latency while maintaining synchronous data arrival between a multiplicity of self-aligning interfaces. Independent self-alignment interfaces may de-skew data bits and have them arrive on a minimum cycle boundary. However, if all the interfaces do not arrive on the same cycle, SMP designs may not function properly. For instance, with a single control chip and multiple data chips on an AMP node, the control chip often sends out controls to the dataflow chips. If the data arriving on the elastic interfaces is not synchronized with the controls, the data is not routed properly. The method employs a calibration pattern to determine the latest cycle that data is received across the elastic interfaces and calculates the target cycle for all the interfaces to match this latest cycle. The target cycle is fed back into the design and the data is received synchronously, also provided is a test to ensure that the data arrives synchronously.
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Chen Jonathan Y.
Meaney Patrick J.
Scarpero, Jr. William J.
Augspurger Lynn L.
Butler Dennis M.
International Business Machines - Corporation
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