Dielectric layer of a memory cell having a stacked oxide sidewal

Details Dielectric layer of a memory cell having a stacked oxide sidewal Dielectric layer of a memory cell having a stacked oxide sidewal

1999-04-13

2000-08-15

Booth, Richard

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438265, 438258, H01L 218247

Patent

active

061035769

ABSTRACT:
A merged two-transistor memory cell of an EEPROM, and method of fabricating the cell, are provided. The memory cell includes a substrate and gate oxide layer formed on the substrate. It also includes a memory transistor having a floating gate and a control gate, and a select transistor having a gate that is shared with the memory transistor. The memory cell is configured so that the shared gate serves both as the control gate of the memory transistor and the wordline of the select transistor. The memory cell further includes a dielectric layer that is disposed between the floating gate and the shared gate. The dielectric layer is defined by an ONO film and a stacked oxide layer. In fabricating the memory cell, the ONO stack film is formed adjacent to the top surface of the floating gate and the stacked oxide layer is formed adjacent to the side surface of the floating gate.

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