Device with self aligned gaps for capacitance reduction

Details Device with self aligned gaps for capacitance reduction Device with self aligned gaps for capacitance reduction

2005-11-30

2008-10-07

Lebentritt, Michael S. (Department: 2829)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C257S333000, C257S340000, C257S758000, C438S637000

Reexamination Certificate

active

07432189

ABSTRACT:
A method for reducing capacitances between semiconductor device wirings is provided. A sacrificial layer is formed over a dielectric layer. A plurality of features are etched into the sacrificial layer and dielectric layer. The features are filled with a filler material. The sacrificial layer is removed, so that parts of the filler material remain exposed above a surface of the dielectric layer, where spaces are between the exposed parts of the filler material, where the spaces are in an area formerly occupied by the sacrificial layer. Widths of the spaces between the parts of the filler material are shrunk with a shrink sidewall deposition. Gaps are etched into the dielectric layer through the shrink sidewall deposition. The filler material and shrink sidewall deposition are removed.

REFERENCES:
patent: 5510645 (1996-04-01), Fitch et al.
patent: 6232214 (2001-05-01), Lee et al.
patent: 6297125 (2001-10-01), Nag et al.
patent: 6605541 (2003-08-01), Yu
patent: 6780753 (2004-08-01), Latchford et al.
patent: 6781192 (2004-08-01), Farrar
patent: 6846741 (2005-01-01), Cooney et al.
patent: 6858153 (2005-02-01), Bjorkman et al.
patent: 6911397 (2005-06-01), Jun et al.
patent: 7008878 (2006-03-01), Hsu et al.
patent: 2003/0219988 (2003-11-01), Shan et al.
patent: 2003/0232474 (2003-12-01), Lai et al.
patent: 2003/0232509 (2003-12-01), Chung et al.
patent: 2004/0002217 (2004-01-01), Mazur et al.
patent: 2004/0072430 (2004-04-01), Huang et al.
patent: 2004/0126705 (2004-07-01), Lu et al.
patent: 2005/0110145 (2005-05-01), Elers
patent: 2006/0160353 (2006-07-01), Gueneau de Mussy et al.
patent: 2007/0122977 (2007-05-01), Kim et al.
International Search Report dated Mar. 27, 2007 from corresponding International Application No. PCT/US2006/044521.
Written Opinion dated Mar. 27, 2007 from corresponding International Application No. PCT/US2006/044521.
International Search Report dated Apr. 24, 2007 from related International Application No. PCT/US2006/044708.
Written Opinion dated Apr. 24, 2007 from related International Application No. PCT/US2006/044708.
International Search Report dated Mar. 20, 2007 from related International Application No. PCT/US2006/044719.
Written Opinion dated Mar. 20, 2007 from related International Application No. PCT/US2006/044719.
U.S. Appl. No., entitled “Device with Gaps for Capacitance Reduction”, by inventors: Sadjadi et al., filed Nov. 30, 2005.
U.S. Appl. No., entitled “Self-Aligned Pitch Reduction”, by inventors: Kim et al., filed Nov. 30, 2005.
Notice of Allowance dated Feb. 19, 2008 for related U.S. Appl. No. 11/558,238.

Affiliated with

Also associated with

Rating

Device with self aligned gaps for capacitance reduction does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Device with self aligned gaps for capacitance reduction, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Device with self aligned gaps for capacitance reduction will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3997811