Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
2002-05-10
2003-09-02
Crane, Sara (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
C257S428000, C438S010000, C438S014000, C438S011000, 23, C324S762010
Reexamination Certificate
active
06614051
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to an apparatus for monitoring the charging of a substrate. More particularly, the invention relates to a device for monitoring charging damage of substrates during semiconductor processing and a method of fabricating such a device.
2. Description of the Background Art
Charged beam and plasma-assisted processes such as plasma enhanced chemical vapor deposition (PECVD), inductive coupled plasma (ICP), and reactive ion etching (RIE), and ion implantation are commonly used in semiconductor processing to enhance the deposition of films or layers on a wafer or to assist in the etching of various material layers.
Unfortunately, these processing methods often cause charges to accumulate on material surfaces and layers that are processed, often to the extent of causing damage to these surfaces and layers. For example, non-uniformities in the plasma or beam may result in the accumulation of high levels of charge on various material layers, resulting in dielectric breakdown of dielectric layers, and thereby compromising the performance of structures being created or processed.
In order to monitor the charge profiles on processed wafers (and thereby and potential damage resulting from processing), the semiconductor industry has employed various means including electrical erasable programmable read only memory (EEPROM) transistor devices.
FIG. 1
shows a schematic cross-section of an EEPROM transistor device for measuring charging. The EEPROM transistor device comprises a semiconductor substrate
22
and an oxide layer
24
disposed atop the semiconductor substrate
22
. A charge collection electrode
10
is disposed atop the oxide layer
24
and coupled to a control electrode
12
. Charge that develops on charge collection electrode
10
, upon exposure to, for example, a plasma, is conducted to control electrode
12
. Floating gate
14
receives charge from control electrode
12
. Due to the asymmetry in the shapes of control electrode
12
and gate
14
, electrons flow more easily from control electrode
12
into gate
14
than in the reverse direction. The threshold voltage required for current flow between a source region
16
and a drain region
18
is a function of the amount of charge that has been developed on the charge collection electrode
10
as well as the resistance of a resistive path
20
between the semiconductor substrate
22
and the charge collection electrode
10
. In order to determine the extent of wafer charging that occurs during a semiconductor process, the EEPROM is placed in a chamber and, as part of a diagnostic wafer, exposed to the process in a “test run” situation. The EEPROM transistor device is subsequently removed from the chamber and the degree of charging is calculated based upon the change in threshold voltage as well as the resistance value of the resistive path.
However, a number of drawbacks are associated with the EEPROM transistor devices. First, the voltage sensing region is limited to a maximum about 20 volts. For applied voltages greater than this value, saturation occurs, and the device is not capable of distinguishing greater degree of charging. Similarly, voltages below about 0.5 to about 1.0 volts are too small to be accurately detected. Second, the EEPROM device is sensitive to ultraviolet (UV) radiation. This is problematic in that if the EPPROM device is placed in an environment containing ultraviolet radiation, as is typically the case for plasma-assisted processes, the reading provided by the device may not be a completely accurate reading that is based solely upon effects of charging. Another serious drawback on the EEPROM device is its inherent complexity. The EEPROM is a transistor device that requires numerous time consuming steps, including masking, ion implantation, among others to create.
Therefore, a need exists for a charge monitoring device that is capable of operating over a wide range of charging conditions, is not sensitive to UV radiation, and is easy to fabricate.
SUMMARY OF THE INVENTION
The disadvantages associated with prior art are overcome by the present invention of an apparatus for a charge monitoring device comprising one or more capacitor-resistor pairs, wherein the one or more capacitor-resistor pairs comprise a resistor and a capacitor connected in series. The capacitor comprises a ferroelectric charge storage layer.
Also provided is a method of forming a charge monitoring device comprising the steps of forming a bottom electrode layer on a substrate, forming a ferroelectric charge storage layer atop the bottom electrode layer, and forming a top electrode layer atop the ferroelectric charge storage layer. The method further comprises forming a hard mask layer atop the top electrode layer, removing portions of the hard mask layer, and removing portions of the ferroelectric charge storage layer as well as portions of the top electrode layer thereon. This exposes portions of the top surface of the bottom electrode layer and allows other portions to remain in contact with the ferroelectric charge storage layer. The method further comprises forming a dielectric material layer atop the portions of the top surface of the bottom electrode layer and atop the hard mask layer and forming a first opening in the dielectric layer above the other portions of the top surface of the bottom electrode layer, the first opening of sufficient depth to expose portions of the top surface of the hard mask layer. The method further comprises forming a second opening in the dielectric layer above the portions of the top surface of the bottom electrode layer, the second opening of sufficient depth to expose a segment of the top surface of the bottom electrode layer. Conductive material is then provided to the first opening and the second opening.
Also provided is a method of measuring a charge accumulation on a semiconductor wafer. The method comprises the steps of positioning a charge monitoring device in a semiconductor wafer production chamber. The charge monitoring device comprises one or more capacitor-resistor pairs having a threshold switching voltage. The one or more capacitor-resistor pairs, comprise a capacitor in series with one or more resistors. The capacitor comprises a ferroelectric charge storage layer. The method further comprises initiating a manufacturing process in the chamber and measuring the charge accumulation within the ferroelectric charge storage layer of the charge monitoring device.
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patent: 11-238774 (1999-08-01), None
Applied Materials Inc.
Bach Joseph
Crane Sara
Im Junghwa
Moser Patterson & Sheridan
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