Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2004-01-30
2008-07-29
Schillinger, Laura M (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S623000, C438S703000
Reexamination Certificate
active
07405147
ABSTRACT:
A method for manufacturing a structure includes providing a structure having an insulator layer with at least one interconnect and forming a sub lithographic template mask on the insulator layer. A selective etching step is used for etching the insulator layer through the sub lithographic template mask to form sub lithographic features near the at least one interconnect. A supra lithographic blocking mask may also be utilized. In another aspect, the method includes forming pinch off sections of sub lithographic size formed in a capping layer on the insulator layer. A semiconductor structure includes an insulator layer having at least one interconnect feature and at least one column formed in the insulator layer. A plurality of sub lithographic features formed on a top portion of the insulator layer and communicating with the at least one column is also provided. The plurality of sub lithographic features have a cross section or diameter less than any of the at least one column. A gap may be prohibited from forming on or near scribe lines or vias.
REFERENCES:
patent: 6265321 (2001-07-01), Chooi et al.
patent: 6346484 (2002-02-01), Cotte et al.
patent: 6358813 (2002-03-01), Holmes et al.
patent: 6451712 (2002-09-01), Dalton et al.
patent: 6495479 (2002-12-01), Wu et al.
patent: 6506660 (2003-01-01), Holmes et al.
patent: 6509623 (2003-01-01), Zhao
patent: 2002/0016058 (2002-02-01), Zhao
patent: 2002/0058394 (2002-05-01), Holmes et al.
patent: 2002/0061633 (2002-05-01), Marsh
patent: 2002/0061646 (2002-05-01), Kan et al.
patent: 2002/0192949 (2002-12-01), Kan et al.
patent: 2003/0073302 (2003-04-01), Huibers
patent: 2005/0167838 (2005-08-01), Edelstein et al.
patent: 2008/0038915 (2008-02-01), Edelstein et al.
patent: 2008/0038923 (2008-02-01), Edelstein et al.
patent: 2008/0093743 (2008-04-01), Yang et al.
V. Arnal, et al., “A Novel SiO2Air Gap Low K for Copper Dual Damascene Interconnect.” Conference Proceedings of the Advanced Metallization Conference 2000, pp. 71-76.
A. P. Li, et al., “Hexagonal Pore Arrays with a 50-420 nm Interpore Distance Formed by Self-Organization in Anodic Alumina.” Journal of Applied Physics, vol. 84, No. 11, Dec. 1, 1998, pp. 6023-6026.
O. Jessensky, et al., “Self-Organization Formation of Hexagonal Pore Arrays in Anodic Alumina.” Journal of Applied Physics, vol. 72, No. 10, Mar. 9, 1998, pp. 1173-1175.
A. P. Li, et al., “Polycrystalline Nanopre Arrays with Hexagonal Ordering on Aluminum.” Journal of Vacuum Science and Technology, vol. 17, No. 4, Jul./Aug. 1999, pp. 1428-1431.
L.G. Gosset, et al., “General Review of Issues and Perspectives for Advanced Copper Interconnections Using Advanced Copper Interconnections Using Air Gaps as Ultra-Low K Material.” IEEE 2003, pp. 65-67.
V. Arnal, et al., “Integration of a 3 Level Cu—SiO2Air Gap Interconnect for Sub 0.1 micron CMOS Technologies.” IEEE 2001, pp. 298-300.
C.T. Black, et al., “Integration of Self-Assembled Diblock Copolymers for Semiconductor Capacitor Fabrication.” Applied Physics Letters, vol. 79, No. 3, Jul. 16, 2001, pp. 409-411.
Z. Liu, et al., “Metal Nanocrystal Memories—Part I: Device Design and Fabrication.” IEEE Transactions on Electron Devices, vol. 49, No. 9, Sep. 2002, pp. 1606-1613.
Colburn Matthew E.
Cooney, III Edward C.
Dalton Timothy J.
Edelstein Daniel C.
Fitzsimmons John A.
Abate Joseph P.
Greenblum & Bernstein P.L.C.
Schillinger Laura M
LandOfFree
Device and methodology for reducing effective dielectric... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Device and methodology for reducing effective dielectric..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Device and methodology for reducing effective dielectric... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3972031