Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2000-10-18
2004-03-16
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S728000
Reexamination Certificate
active
06708305
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
This invention relates to the field of testing semiconductor circuits. More specifically, the invention relates to deterministic random Logic Built In Self Test (LBIST).
2. Background Art
Computer chips have become extremely complex: Millions of logic devices can be made to fit on one chip. Because of this complexity, it is essential that these chips be tested. Thus, as part of the millions of devices that can make up a semiconductor chip, there are devices added directly to the chip to help with testing. These devices perform an internal type of testing, which tests the inner workings of the chip. Generally, an external testing device can read the results of these tests to determine if the chip has any errors in its circuitry.
One popular testing method in this vein is called Logic Built In Self Test (LBIST). One way of performing LBIST is to have a pseudorandom pattern generator generate a variety of pseudorandom patterns that can be used to test logic devices. This testing methodology is often called random LBIST.
Theoretically, a chip could be tested by inputting, to the various logic devices on the chip, every possible input combination. Every output created by these inputs would then be viewed to determine if the correct output was captured. This would be perfect fault coverage. However, an exhaustive test involves such an extensive number of test patterns that it is expensive to apply. Early when there are many faults that are untested, random LBIST is relatively productive. However, as fault coverage climbs and fewer untested faults remain, random LBIST begins generating a high ratio of unproductive tests. The fault coverage obtainable with random LBIST typically tails off and stalls before the fault coverage is reached that is needed to ensure desired product quality. Consequently, many of the difficult faults are left untested by random LBIST. This problem has precluded random LBIST from obtaining the desired fault coverage and test quality level within a reasonable number of test patterns. So, while random LBIST is effective in testing many faults, it is not a complete test.
A cost-effective approach to this problem is to simulate a representative model of possible faults in the device and determine which inputs or care bits are required to test each of these faults. Tests are generated that provide these required inputs, and the corresponding faults may then be marked as being covered. Historically, deterministic stored pattern testing has avoided the problems of random LBIST by determining these required inputs and using the inputs to test the computer chip. Deterministic stored pattern testing entails analyzing the logic devices on the computer chip and determining the inputs that would test particular faults. For example, to adequately test a three-input NAND gate, all eight combinations of inputs would need to be tested. To test a “stuck at one” fault, however, only one of these combinations—setting all three inputs to ones or a high voltage—need be input to the NAND gate. When all three inputs are a high voltage, the output of the NAND gate should change from a one to a zero. If the output stays a one (a high voltage), the NAND gate is not functioning properly. Deterministic stored pattern testing attempts to find and test these types of particular errors.
To perform deterministic stored pattern testing, the precalculated, stored deterministic patterns are downloaded from the tester into the chip. These deterministic patterns contain the important bits to test particular faults, and they contain these important bits in the correct positions. For instance, to test a stuck at one fault for a three-input NAND gate, the tester needs to download the three important, high bits at the correct locations. These important bits are known as care bits. Generally, logic devices on the computer chip are organized into “scan channels” that allow information to be moved through the logic devices. Each scan channel is a series of logic latches. The tester must download the care bits into the scan channels so that the bits are correctly positioned in the scan channels to adequately test the particular fault.
Deterministic testing is very beneficial, as it discovers faults that LBIST simply will not discover with a reasonable number of tests. A problem with deterministic testing, however, is that the scan bits must be written onto the chip and the results must be read off of the chip. Unlike in LBIST, where both test bits and result bits are generated on chip, all of the test bits for deterministic testing are generated off chip and the result bits are communicated off chip. The number of test bits can be very large, and the number of result bits can be quite high. Downloading the test bits and reading the result bits take a tremendous amount of bandwidth and can be time consuming.
What is needed is a way of performing deterministic testing without the high bandwidth required by off chip deterministic testing, yet also still retaining the benefits of random LBIST.
DISCLOSURE OF INVENTION
To overcome these problems, deterministic random Logic Built In Self Test (LBIST) is disclosed that applies Deterministic Stored Pattern Tests (DSPTs) by using random LBIST. Basically, the present invention selects the appropriate pseudorandom pattern for use with a scan cycle that needs care bits. The scan cycle may be a current or future scan cycle. In particular, the present invention determines care bits for a particular scan cycle. A pseudorandom pattern is generated that is then aligned with the particular scan cycle. If the pseudorandom pattern contains the care bits, with the correct values and in the proper positions within the pattern, this alignment properly tests one or more logic devices.
There are various techniques used to align a pseudorandom pattern, which contains the correct values in the correct positions for the care bits, with the scan cycle to ensure that a logic device is properly tested. For instance, pseudorandom patterns may be skipped until the pseudorandom pattern is found that has the correct care bits for the current scan cycle. Alternatively, care bits for a future scan cycle may determined and if a current or intermediate pseudorandom pattern contains the correct care bits for the future scan cycle, the current pseudorandom pattern may be output until and through the future scan cycle. This can be done by starting at the current scan cycle and “looking forward” to the future scan cycle or by starting at the future scan cycle and “looking backward” to the current scan cycle. Additionally, care bits for a future scan cycle may determined and a pseudorandom pattern generator (PRPG) perturbed, preferably through the use of an input bit, to force the pseudorandom pattern, at the future scan cycle, to contain the appropriate care bits in the appropriate positions. Also, the care bit requirements of multiple scan cycles in the future can be evaluated in determining how a PRPG can be perturbed.
The present invention takes into account that most scan bits are “don't care” bits. The don't care bits can be assigned either a zero or a one state, without loss of quality, in the course of manipulating a pseudorandom pattern generator or channel controls when delivering the required care bits.
Because the on chip pseudorandom pattern generators are being used to create the pseudorandom patterns, the high bandwidth cost of a DSPT are reduced or eliminated. The DSPT equipment may be used in a slightly different manner than for normal DSPT, and the computer chip has to have one or more clock gates that help to align the pseudorandom patterns with the appropriate scan cycles. The improvements result in much lower test times for very little increased costs.
REFERENCES:
patent: 5173906 (1992-12-01), Dreibelbis et al.
patent: 5361264 (1994-11-01), Lewis
patent: 5369648 (1994-11-01), Nelson
patent: 5479414 (1995-12-01), Keller et al.
patent: 5546406 (1996-08-01), Gillenwater et al.
patent: 5640402 (1997-06-01), Motika et al.
p
Farnsworth L. Owen
Keller Brion L.
Koenemann Bernd K.
Koprowski Timothy J.
Snethen Thomas J.
Chaudry Miytaba
De'cady Albert
International Business Machines - Corporation
Schmeiser Olsen & Watts
Walsh Robert A.
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