Detecting interport faults in multiport static memories

Details Detecting interport faults in multiport static memories Detecting interport faults in multiport static memories

1999-07-28

2003-04-15

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

Reexamination Certificate

active

06550032

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
Not applicable.
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not applicable.
FIELD OF THE INVENTION
The present invention relates generally to memory devices and particularly to multiport static memory devices. More particularly, the present invention relates to detecting interport faults in static memory devices.
BACKGROUND OF THE INVENTION
Multiport Architecture
Fast, efficient testing is an important step in manufacturing memory chips, and the price paid for recent advances in semiconductor technology has been a lengthier and more complicated testing process. A common feature of current memories is the presence of multiple “ports,” or gateways that allow data to be read from and/or written to the memory. The ports on a multiport memory are designed to function independently, allowing the reading or writing of data in multiple locations at the same time. Prior memories, which had a single memory port, could only read or write data in one memory location at a time. Multiple ports thus increase memory throughput, or the speed at which data can be transferred to and from memory.
FIG. 1
illustrates a representative multiport memory device
150
, comprising an array of memory cells
100
,
101
,
109
,
110
,
111
,
119
,
190
,
191
and
199
. As shown in
FIG. 1
, the cells are organized into R rows and C columns, where R and C can be any values. Cells
100
and
101
represent the first two columns of the first row, and cell
109
represents the last (or C−1
th
) column of the first row. Similarly, cells
110
,
111
, and
119
represent the first, second, and last columns of the second row. In the final (or R−1
th
) row, cells
190
,
191
, and
199
occupy the first, second, and last columns, respectively. Each memory cell is capable of storing an electric charge, and the charges can be manipulated to store and recall data through the use of special control circuitry (not shown) in the memory
150
. Each memory cell can represent one of two values, depending on whether or not the cell holds a charge. The values 1 and 0 are often used to represent the charged and uncharged states, respectively, although the reverse may be true. Because the cells can hold either of two possible values, the memory device
150
is called a “binary” device, and the cell data values are known as binary digits, or “bits.”
To fetch and store the data values, the memory device
150
includes “word line” and “bit line” signals that couple to the cells. The word line signals connect cells in the same row and are used to activate the cells along one row at a time. The bit line signals connect cells in the same column and are used to carry data to and from the activated cells. In a multiport device, each port has its own word lines and bit lines. The memory device
150
in
FIG. 1
is shown with P ports, where P can be any number but is typically less than or equal to 11 under current technology.
The first port includes a first word line W
10
that connects the cells
100
,
101
, and
109
in the first row; a second word line W
11
that connects the cells
110
,
111
, and
119
in the second row; and additional word lines for the other rows, including a word line W
P(R−1)
that connects the cells
190
,
191
, and
199
in the final row. The first port also comprises a first bit line B
10
that connects the cells
100
,
110
, and
190
in the first column; a second bit line B
11
that connects the cells
101
,
111
, and
191
in the second column; and additional bit lines for the remaining columns, including a bit line B
P(C−1)
that connects the cells
109
,
119
, and
199
in the final column. To read data from the first row of cells through the first port, for example, the word line W
10
is activated. In response to activating the word line W
10
, cells
100
and
101
place their data values onto bit lines B
10
and B
11
, respectively. Similarly, the other cells in the first row drive their bit lines on the first port with the stored data, including cell
109
, which drives bit line B
1(C−1)
with the data value stored in cell
109
.
The word lines and bit lines also can be used to store data in the cells. To write data to the cells in the second row through the first port, for example, the word line W
11
is asserted to activate the cells in the second row, including cells
110
,
111
, and
119
. At the same time, the values being stored are placed on the bit lines belonging to the first port, including bit lines B
10
, B
11
, and B
1(C−1)
. In response, the cells on the second row store the data encoded by the bit lines. Cell
110
thus stores the value of bit line B
10
, cell
111
stores the value of bit line B
11
, and cell
119
stores the value of bit line B
1(C−1)
.
Similarly, the remaining ports include word lines and bit lines for accessing the memory cells. Ideally, one port can access any row of cells while another port is accessing another row of cells without interference between the two ports, since the ports do not share word lines and bit lines. In reality, however, manufacturing defects can cause one port to interfere with another port, affecting the data values that are read or written through either port. Other manufacturing defects can cause individual cells to interact unreliably. Memory defects are generally classified as cell faults, addressing faults, read/write logic faults, and interport faults.
Cell Faults
Cells faults generally include defects known as unlinked faults, coupling faults, linked faults, neighborhood pattern sensitive faults, and complex coupling faults. Unlinked faults represent faults that occur in specific cells, without regard to a particular port or to the values of nearby cells. Types of unlinked faults include stuck-at faults, in which a cell holds a particular data value permanently; transition faults, in which a cell cannot make a transition between two values; and data retention faults, in which a cell fails to retain the correct logic value after a period of time. Table I summarizes unlinked faults.
TABLE I
Unlinked cell faults
Name
Description
Stuck-At Fault
Cell holds either a 0 or a 1 permanently.
Transition Fault
Cell cannot transition from 1 to 0,
or cell cannot transition from 0 to 1.
Data Retention Fault
Cell loses data after a period of time.
Coupling faults represent faults in which writing a value to one cell influences the data value of another cell. Coupling faults include inversion faults, in which inverting the value of a first cell inverts the value of a second cell; idempotent faults, in which inverting the value of a first cell causes a particular value (either a 1 or a 0) to be stored in a second cell; bridging faults, in which two cells are shorted together; state faults, in which a first cell is forced to a certain value if and only if a second cell holds a particular value; and disturbance faults, in which a first cell changes value in response to a read or write operation in a second cell. Bridging faults can behave as one of two types: AND-type or OR-type. In an AND-type fault, a first cell is forced to 0 if and only if a 0 is stored in second cell. In an OR-type fault, a first cell is forced to 1 if and only if a 1 is stored in a second cell. Table II summarizes coupling faults.
TABLE II
Coupling cell faults
Name
Description
Inversion
Inverting the value of one cell causes an inversion
Fault
in another cell.
Idempotent
Inverting the value of one cell causes another cell to hold a
Fault
specific value (either a 1 or a 0).
Bridging
Storing a 0 in a cell causes another cell to hold a 0, but
Fault
storing a 1 in the cell does not affect the other cell
(AND-type). Storing a 1 in a cell causes another cell to
hold a 1, but storing a 0 in the cell does not affect
the other cell (OR-type).
State
A first cell is forced to either 1 or 0 if and only if a second
Fault
cell holds a particular value.
Disturbance
Reading or writing one cell inverts the value of another cell.
Fault
Other cell faults include linked faults, neighb

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