Design structure for final via designs for chip stress...

Details Design structure for final via designs for chip stress... Design structure for final via designs for chip stress...

2008-03-07

2008-10-21

Garber, Charles D. (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S612000, C438S613000, C257SE21476

Reexamination Certificate

active

07439170

ABSTRACT:
A design structure to provide a package for a semiconductor chip that minimizes the stresses and strains that arise from differential thermal expansion in chip to substrate or chip to card interconnections. An improved set of design structure vias above the final copper metallization level that mitigate shocks during semiconductor assembly and testing. Other embodiments include design structures having varying micro-mechanical support structures that further minimize stress and strain in the semiconductor package.

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