Design and a novel process for formation of DRAM bit line and ca

Details Design and a novel process for formation of DRAM bit line and ca Design and a novel process for formation of DRAM bit line and ca

1998-04-01

1999-12-28

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438637, H01L 218242

Patent

active

06008085&

ABSTRACT:
A process for fabricating a DRAM cell has been developed, in which two interlaced patterns, each comprised of capacitor node contact holes and bit line contact holes, are independently created, each using a specific photolithographic mask, and a specific photolithographic procedure. The two interlaced patterns allow the creation of the capacitor node contact images, and the bit line contact holes images, to be formed in a thin polysilicon layer, with minimum spacing between contact images. Capacitor node contact holes, as well as bit line contact holes, are than formed in an insulator layer, via a dry etching procedure, using the patterned thin polysilicon layer as a mask. The use of specific masks, or of the interlaced pattern, allows the minimum spacing, between a capacitor node contact hole, and a bit line contact hole, to be limited only by the overlay between photolithographic masks.

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patent: 5403766 (1995-04-01), Miyake
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patent: 5573634 (1996-11-01), Ham
patent: 5866453 (1999-02-01), Prall et al.
patent: 5930621 (1999-07-01), Kang et al.

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