Depletion mode MOS capacitor with patterned V.sub.T implants

Details Depletion mode MOS capacitor with patterned V.sub.T implants Depletion mode MOS capacitor with patterned V.sub.T implants

1999-03-19

2000-08-15

Hardy, David

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438548, 438549, 438217, 438241, 438250, 438251, 438275, 438276, 438289, H01L 218238

Patent

active

061035610

ABSTRACT:
A method for making a memory cell (10) in a process in which both an n-channel MOS transistors (12) and a p-channel transistor (44) are formed in a semiconductor substrate (30) is presented. The method includes implanting an impurity (40) into a region of the substrate (30) to form a part of a depletion NMOS memory capacitor (21) to be associated with the n-channel MOS memory transistor (12). The implant is performed concurrently with a patterned implant with the same impurity to adjust the threshold and punch-through of the p-channel transistor (44).

REFERENCES:
patent: 4131983 (1979-01-01), Matzen
patent: 4696092 (1987-09-01), Doering et al.
patent: 4950617 (1990-08-01), Kumagai et al.
patent: 5071784 (1991-12-01), Takeuchi et al.
patent: 5238860 (1993-08-01), Sawada et al.
patent: 5484739 (1996-01-01), Lee et al.
patent: 5736415 (1998-04-01), Chang et al.

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