Depleted poly mosfet structure and method

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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Details

C438S231000, C438S232000, C438S307000

Reexamination Certificate

active

06171918

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to processes for fabricating metal oxide semiconductor field effect transistor (MOSFET) structures and more particularly to MOSFET structures which include lightly doped polysilicon gates, operating at high operating voltages, and MOSFET structures which include more heavily doped polysilicon gate structures which operate at low operating voltages.
2. Description of the Related Art
As the gate oxide thickness decreases in today's advanced complementary metal oxide semiconductor (CMOS) technologies, the maximum voltage (Vmax) allowed across the gate oxide also decreases. The decrease in Vmax makes interfacing with previous technologies which have higher supply voltages more difficult.
A conventional solution to interface previous technologies which have higher supply voltages involves using circuit techniques to step down the voltage which is seen across the oxide or creating a dual oxide process which supports a higher Vmax. Using circuit techniques to step down the voltage increases circuit complexity and decreases overall chip speed. Using a dual oxide process increases the processing cost and complexity.
Conventional methods form CMOS devices on a single wafer. Each of the CMOS devices includes a polysilicon gate and a thin gate oxide between the polysilicon gate and the substrate. Ions are implanted to dope the polysilicon gate and the adjacent source and drain structures.
Conventionally, selected polysilicon gates are protected with a sacrificial layer and the remaining polysilicon gates are subjected to a first ion implantation of the extension or lightly doped drain, such that only the polysilicon gates which are exposed receive the lightly doped drain implant.
Conventional processes then dope other polysilicon gates using the source-drain implant. In such a second ion implantation step, selected polysilicon gates are protected with another sacrificial layer and the exposed polysilicon gates are subject to the second ion implantation. This repetitive masking-implantation process produces some polysilicon gates with lighter doping and other polysilicon gates with heaver doping. The blocking of the second ion implantation produces lightly doped gates in the blocked devices, which are sometimes referred to as poly depleted gates. The lightly doped or undoped polysilicon gates accommodate higher voltages due to the added poly depletion which occurs.
While such conventional methods simultaneously produce CMOS chips which can handle high voltages and CMOS chips which can handle low voltages, the conventional methods require additional processing steps to deposit and remove additional sacrificial layers and require additional implantation steps.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a structure and method for simultaneously manufacturing CMOS chips which include heavily doped and lightly doped polysilicon gates (which can accommodate high and low voltages) without requiring additional processing steps for the lightly doped gates. More specifically, with the invention the polysilicon gate is doped at the same time when the extension and source/drain are implanted, to eliminate the need for additional masking and ion implantation steps.
The invention includes a method for doping a semiconductor transistor, the semiconductor transistor including a gate region, a source region adjacent the gate region and a drain region adjacent the gate region and opposite the source region, the method comprising exposing the gate region to a first ion implantation and shielding the gate region from a second ion implantation step.
One of the first ion implantation and the second ion implantation comprises a lower dose implant than the other. The shielding step comprises a step of forming a protective sacrificial layer over the gate region. The first ion implantation and the second ion implantation comprise steps of doping the gate region, the source region and the drain region with an impurity. The impurity comprises arsenic.
The invention also includes a method of simultaneously forming high voltage transistors and low voltage transistors on a semiconductor wafer comprising steps of forming an oxide layer on a substrate of the wafer, forming a polysilicon layer on the oxide layer, selectively removing the polysilicon layer and the oxide layer from the substrate to form gate regions comprising the polysilicon layer and the oxide layer, source regions adjacent the gate regions, and drain regions adjacent the gate regions and opposite the source regions, implanting a first concentration of ions to the gate regions, the source regions, and the drain regions, shielding a first group of the gate regions and leaving a second group of the gate regions exposed and implanting a second concentration of ions to the second group of the gate regions, the source regions and the drain regions.
The first concentration is lower than the second concentration. The first group of gates comprise gates of the high voltage transistors and the second group of gates comprise gates of the low voltage transistors. The high voltage transistors and the low voltage transistors comprise field effect transistors. The shielding step comprises a step of forming a protective sacrificial layer over the first group of the gate regions. The step of implanting a first concentration and the step of implanting a second concentration comprise steps of doping the gate regions, the source regions and the drain regions with an impurity.
The invention also includes a method for preventing silicide spiking in semiconductor transistors, the semiconductor transistors having gate regions, source region adjacent the gate regions and drain region adjacent the gate regions and opposite the source regions, the method comprising a step of forming a silicide block adjacent the gate regions. The step of forming a silicide block comprises a step of depositing a nitride layer adjacent the gate regions.
Thus, by using only the extension or lightly doped drain implant to lightly dope the poly gate in the depleted devices, the invention does not require the additional masks required in the conventional processes.
The lighter doped gate causes poly depletion to occur, which increases the maximum voltage (Vmax) which the oxide can accommodate before suffering damage. Therefore, with the invention, high voltage and low voltage MOS devices can be simultaneously manufactured in a process which does not require the additional mask deposition and removal steps required with other depleted polysilicon device processes.


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