Multi-bank ESDRAM with cross-coupled SRAM cache registers

Details Multi-bank ESDRAM with cross-coupled SRAM cache registers Multi-bank ESDRAM with cross-coupled SRAM cache registers

1998-10-23

2001-06-19

Verbrugge, Kevin (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

Reexamination Certificate

active

06249840

ABSTRACT:

The present invention relates generally to integrated circuit memory devices. More particularly the present invention relates to a memory device, and an associated method, having a DRAM (dynamic random access memory) memory portion and at least two SRAM (static random access memory) cache registers in which data stored at selected rows of the DRAM memory array can be cached as a result of a read command.
In an exemplary implementation, the invention is embodied in a multi-bank ESDRAM (enhanced synchronous dynamic random access memory) having a plurality of DRAM banks and a plurality of SRAM cache registers. The SRAM cache registers are able to store data retrieved from any of the DRAM banks of any ESDRAM of the multi-bank ESDRAM during a read page operation and thereafter burst the data onto a data bus. The read page operation from any of the DRAM banks to any of the SRAM cache registers is effectuated utilizing an already-existing SRAM command set.
Pages of data stored at a single DRAM bank can be cached at any of the SRAM cache registers. By permitting more than one SRAM cache register to be associated with a single DRAM bank, data read from a single DRAM bank during successive read operations need not overwrite data previously read from the DRAM bank to a single SRAM cache register.
BACKGROUND OF THE INVENTION
Advancements in digital technologies have permitted the development and implementation of many new products. Products pertaining to, and including, digital processing circuitry are exemplary of products possible as a result of such advancements.
Repetitive functions can be carried out by digital processing circuitry at rates significantly more rapidly than the manual performance of such functions. The rapid rates at which the digital processing circuitry is able to repeatedly perform such functions have permitted activities previously considered impractical, to be readily implementable.
During the effectuation of functions by the operation of digital processing circuitry, data is sometimes read from, and written to, memory locations of a memory device. For instance, a digital computer system includes a central processing unit and a computer main memory. The computer main memory provides storage locations to which to write data, and from which to read data. Asynchronous DRAM (dynamic random access memory) integrated circuit devices are sometimes used to form the computer main memory. DRAM devices provide a relatively inexpensive memory at which to store relatively large amounts of data. SRAM (static random access memory) integrated circuit devices sometimes also form the computer main memory, or portions thereof. Relatively quick access is permitted to the memory locations of an SRAM integrated circuit device as a high-speed, locally-accessed copy of the memory available to the central processing unit of the computer system. However, SRAM devices are relatively more costly than DRAM devices.
An ESDRAM (enhanced synchronous dynamic random access memory) is formed of both a DRAM component portion and an SRAM component portion. Because of the dual nature of an ESDRAM, an ESDRAM provides the advantages of a DRAM memory device and also the advantages of an SRAM device. Namely, the cost advantages of a DRAM are provided by the DRAM component portion of the ESDRAM, and the speed advantages of the SRAM are provided by the SRAM component portion of the ESDRAM. The SRAM component portion of an ESDRAM provides a cache at which a row, also called a “page”, can be stored during execution of a read or write operation. Multi-bank ESDRAM memory devices are available having multiple numbers of DRAM banks, each having an associated SRAM cache, at which digital data can be written and read.
In conventional multi-bank ESDRAM devices, a particular SRAM cache is associated with a particular DRAM memory bank. When data is to be read from, or written to, a particular row of a selected DRAM memory bank, the data is conventionally cached in the SRAM cache associated with the DRAM bank in a direct mapping operation. Because of the speed advantages associated with SRAM devices, if a manner could be provided by which to associate more than one SRAM device with a single DRAM memory array, improved memory retrieval times would be possible. If, in a multi-bank, ESDRAM device, for instance a manner could be provided by which to permit access between a single DRAM bank and the SRAM caches associated with other DRAM banks of the multi-bank device, improved rates of data retrieval operations would be possible.
It is in light of this background material related to integrated circuit memory devices that the significant improvements of the present invention have evolved.
SUMMARY OF THE INVENTION
The present invention, accordingly, advantageously provides a memory device, and an associated method, having at least one DRAM memory array and at least two SRAM registers. Data stored in selected rows of the DRAM memory array can be cached in any of the SRAM registers during a read operation.
In one aspect of the present invention, pages of data stored at a single DRAM bank are retrieved during execution of a read operation and cached in any selected SRAM cache register. Selection to which of the SRAM caches the data is provided pursuant to a read operation is made utilizing an already-existing command set.
In one implementation, a multi-bank ESDRAM is provided. The multi-bank ESDRAM includes a plurality of, i.e., an N-number of DRAM banks and a plurality of, i.e., an N-number of, SRAM cache registers. The SRAM cache registers are able to store data retrieved from any of the DRAM banks of any ESDRAM of the multi-bank ESDRAM during a read page operation. Pages of data read during a read operation are thereby capable of being cached in any of the N-number of cache registers from any of N-number DRAM banks of the multi-bank device. Because the already-existing SRAM command set is utilized to effectuate the read operation, a separate command set is not required to accomplish the associativity. In the exemplary implementation, a bus is provided for interconnecting the SRAM cache registers of the respective ESDRAM devices to provide the pages of data to any selected SRAM cache register.
In these and other aspects, therefore, a memory device, and an associated method, is provided for storing indications of digital data therein. A first DRAM bank is formed of rows and columns of DRAM memory locations and defines a first memory array. A first SRAM register is formed of at least a row of SRAM memory locations capable of caching data of at least a portion of a selected row of the DRAM memory locations of the first DRAM bank responsive to a read command to read the data of the portion of the selected row of the DRAM memory locations of the first DRAM bank to the first SRAM register. A second SRAM register is also formed of at least a row of SRAM memory locations and is also capable of caching data of at least a portion of a selected row of the DRAM memory locations of the first DRAM. Data cached at the second SRAM is responsive to a read command to read the data of the portion of the selected row of the DRAM memory locations of the first DRAM bank to the second SRAM register.


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patent: 6072741 (2000-06-01), Taylor

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