Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-11-20
2003-10-21
Cao, Phat X. (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S271000, C438S589000, C438S268000, C438S212000, C257S328000, C257S329000, C257S330000, C257S335000
Reexamination Certificate
active
06635535
ABSTRACT:
FIELD OF THE INVENTION
This invention relates in general to semiconductor devices and, in particular, to MOSFET devices and processes for forming them.
BACKGROUND
Trench MOSFET structures are particularly useful for low-voltage power MOSFET devices. An existing dense trench structure
10
is shown in FIG.
1
. The structure uses self-alignment technology of the trench etch and for recessing the polysilicon
22
within the etching. The dense trench MOSFET
10
includes a drain metal
30
on one surface of an N+ substrate
26
. A lightly doped N-type epitaxial region
24
is grown on the substrate
26
. The epitaxial layer receives a p-well diffusion
20
followed by N+ implants that form source regions
14
. A P+ body region
17
is provided between the source implants that form source regions
14
. A source metal
12
contacts the N+ source regions
14
and the P+ body region
17
. A trench structure includes a sidewall oxide
16
that lines the trench. Within the trench there is a highly conductive layer of polysilicon
22
. The polysilicon layer is covered with a dielectric, typically borophosphorosilicate glass (BPSG)
18
. In operation, when a voltage is applied to the polysilicon gate electrode
22
, the current flows in a vertical direction between the source regions
14
and the drain
30
along the channel adjacent the sidewalls of the trench.
The structure
10
shown in
FIG. 1
provides for a relatively dense trench structure in the MOSFET power device. The structure uses self-alignment technology for the trench etch and for the polysilicon recess etch. Thereafter, the device is subject to an etching of the BPSG. That etch ensures that there will be enough material removed to establish a good connection to the gate
22
as well as to the source contact
14
.
The structure
10
shown in
FIG. 1
in its intended process eliminates the need for photo alignments between the source contact and the gate. Such alignments are generally critical steps in conventional MOSFET designs. Nevertheless, the structure
10
of
FIG. 1
has two deficiencies. First, the entire active area of the surface of the device is subject to the BPSG etch back. The etching of the BPSG layer
18
can result in large areas on the surface that are subject to damage, defects and contaminants. Second, the gate-to-source capacitance is high due to the component of the polysilicon layer
22
, BPSG layer
18
and the overlying source metal layer
12
.
As a result, the process to formulate the structure
10
requires that both the BPSG and polysilicon recess etch must be accurately controlled. Otherwise, the devices will fail. Device failure will normally be due to the gate-to-source leakage if the BPSG
18
is over-etched. It is also possible that metal step coverage of layer
12
over the recessed area can be adversely affected by over-etching the BPSG layer
18
. If the polysilicon layer
22
is over-etched, the device may fail because no inversion layer will form in the channel region. In addition, the BPSG etch that is used to open the source contact region is difficult to control due to the different substrate topography in the mesa trench and etch regions. Finally, those additional etches may cause additional damage and defects in the devices that could degrade the performance and the reliability of the devices.
SUMMARY
The deficiencies and drawbacks of the structure
10
in
FIG. 1
are overcome by the structure and the methods described herein. In the broader aspects of the invention, both the polysilicon and the BPSG recessed etches can be substantially minimized. Since neither the BPSG layer nor the polysilicon layer is excessively etched, there are less defects and damage to each layer. In addition, a high channel density and lower on-state resistance (RDSON) can be obtained by the methods of the invention. In a low-voltage trench MOSFET (typically less than 60 volts), channel resistance is a dominant component of the total RDSON. In this new structure and process, the source contact area is limited and the spreading resistance between the contact opening and source metal must be minimized. This is accomplished by forming a highly-conductive silicide such as titanium silicide or platinum silicide over the exposed source regions.
REFERENCES:
patent: 4767722 (1988-08-01), Blanchard
patent: 5973368 (1999-10-01), Pearce et al.
patent: 6051468 (2000-04-01), Hshieh
patent: 6252277 (2001-06-01), Chan et al.
patent: 6262439 (2001-07-01), Takeuchi et al.
patent: 2001/0048131 (2001-12-01), Hurkx et al.
Dolny Gary M.
Hao Jifa
Ridley Rodney S.
Cao Phat X.
Fairchild Semiconductor Corporation
Le Thao X.
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