Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-02-26
2002-03-19
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S725000, C714S730000
Reexamination Certificate
active
06360343
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a semiconductor test system which generates test signals for testing electronics devices, and more particularly, to an event based semiconductor test system for producing events of various timings to be used to evaluate a semiconductor device under test wherein the timing of each of the events is defined by a time length from the previous event.
BACKGROUND OF THE INVENTION
In testing semiconductor IC devices by a semiconductor test system, such as an IC tester, a semiconductor IC device to be tested is provided with test signals at its appropriate pins at predetermined test timings. The IC tester receives output signals from the IC device under test generated in response to the test signals. The output signals are strobed, i.e., sampled by strobe signals with predetermined timings or delay times to be compared with expected data to determine whether the IC device functions correctly.
Traditionally, timings of the test signals and strobe signals are defined relative to a tester rate or a tester cycle of the semiconductor test system. Such a test system is sometimes called a cycle based test system. An example of timing relationships in such a cycle based test system is shown in
FIGS. 1A-1E
. In a cycle based test system, the semiconductor device (DUT) is tested by providing a cycled pin pattern vectors at a programmed data rate (tester cycle) to a formatter with timing edges to produce the desired wave forms (test signals) or strobe signals.
In the example of
FIG. 1
, based on a reference (system) clock shown in
FIG. 1A
, a cycle based test system produces tester cycles of FIG.
1
B. The test system generates test signals of
FIGS. 1C and 1D
and a strobe signal of FIG.
1
E. The timings of the test signals and strobe signal are defined with reference to the tester cycle of FIG.
1
B. For example, the timings of the test signal of
FIG. 1C
are defined by the time lengths of T
1
, T
2
and T
3
, respectively, with reference to start edges of the corresponding tester cycles. The timings of the test signal of FIG.
1
D and strobe signal of
FIG. 1E
are similarly defined relative to the tester cycles.
As noted above, generally, the various timings of the tester cycle, test signals and strobe signals, such as in the above example, are generated based on the reference clock as shown in FIG.
1
A. The reference clock is produced by, for example, a crystal oscillator provided in the IC tester. When the required timing resolution in an IC tester is equal to or an integer multiple of the highest clock rate (shortest clock cycle) of a reference clock oscillator, timing signals can be generated by simply dividing the reference clock by a counter or a divider and synchronizing the divided output with the reference clock.
However, IC testers are usually required to have timing resolution higher than the highest clock rate, i.e., the shortest time period, of a reference (system) clock. For example, in the case where a reference clock available in the market is 10 ns (nanosecond), but an IC tester needs to have timing resolution of 0.1 ns. Furthermore, the IC testers dynamically change such various timings in a cycle by cycle basis based on a test program.
To generate such timing signals with the timing resolution higher than the reference clock rate, it is known in the prior art that such timings are described by timing data in a test program. The timing data is a combination of an integer multiple of the reference clock time interval and a fraction of the reference clock time interval. Such timing data is stored in a timing memory and read out at each cycle of the test cycle. Thus, in each test cycle, test signals and strobe signals are generated with reference to the test cycle, such as a start point of each cycle, based on the timing data.
There is another type of test system called an event based test system wherein the desired test signals and strobe signals are produced by data from an event memory directly on a per pin basis. As of today, an event based test system is not actualized in the market but under investigation. In an event based test system, events, which are any changes in the logic state, such as rising and fallings of test signals and strobe signals, are defined with respect to time length from reference time points. Typically, such reference time points are timings of previous events such as shown in the example of
FIGS. 3A-3K
. For producing high resolution timings, the time length between the events is defined by a combination of an integer multiple of a reference clock time interval and a fraction of the reference clock time interval.
In the example of
FIG. 3
, the timing of Event
1
is 1({fraction (3/16)})ns (nanosecond) from a start time “0” as in FIG.
3
I. The timing of Event
2
is 1({fraction (7/16)})ns apart from Event
1
as shown in FIG.
3
J and the timing of Event
3
is 1({fraction (8/16)})ns after Event
2
as shown in FIG.
3
K. More details of the timing generation in the event based test system will be provided later with respect to the present invention.
In an event based test system, since the timing data in a timing memory (event memory) does not need to included each and every test cycle data, a format of the timing data is significantly simplified, which also simplifies a process for producing the test signals and strobes. In the event based test system, the timing data for each event stored in an event memory is expressed by a time difference between the current event and the last event. Since such a time difference between the adjacent events is very small, a size of the data in the memory can also be small, resulting in the reduction of the memory capacity.
Moreover, in computer aided design (CAD) systems widely used today for designing a semiconductor device such as an LSI and VLSI, most logic simulators in the CAD system utilizes event based test signals for evaluating the semiconductor device. Therefore, an event based test system enables a more direct linking ability between the design data produced by the CAD system in the design stage and the test signals to be generated using the design data.
SUMMARY OF THE INVENTION
Therefore, it is an object of the present invention to provide an event based semiconductor test system for producing test signals and strobes based on event data stored in an event memory to evaluate a semiconductor device.
It is another object of the present invention to provide an event based semiconductor test system wherein the timing of each of the events is defined by a time length (delta time) from the last event.
It is a further object of the present invention to provide an event based semiconductor test system for producing test signals and strobes based on event information whose time length (delta time) from a previous event is defined by a combination of an integer multiple of a reference clock period and a fraction of the reference clock period.
It is a further object of the present invention to provide an event based semiconductor test system for producing test signals and strobes directly with the use of the timing data in an event memory.
It is a further object of the present invention to provide an event based semiconductor test system which is capable of directly using data produced by a test bench of a CAD system in a design stage of the semiconductor device under test for generating test signals and strobes.
The present invention is an event based test system for testing an electronics device under test (DUT) by supplying a test signal to the DUT and evaluating an output of the DUT at a timing of a strobe signal. The event based test system includes: an event memory for storing timing data of each event formed with an integer multiple of a reference clock period (integral part data) and a fraction of the reference clock period (fractional part data) wherein the timing data represents a time difference between two adjacent events, an address sequencer for generating address data for accessing the event memory to read out the timing data therefrom, a
Advantest Corp.
Amanze Emeka J.
De'cady Albert
Muramatsu & Associates
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