Delay fault testing with IEEE 1149.1

Details Delay fault testing with IEEE 1149.1 Delay fault testing with IEEE 1149.1

1998-12-22

2001-09-04

Tu, Christine T. (Department: 2784)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C712S227000

Reexamination Certificate

active

06286119

ABSTRACT:

TECHNICAL FIELD
The present invention relates to interconnect delay fault test using the IEEE 1149.1 standard test access port (TAP) operations.
BACKGROUND INFORMATION
With the increasing demands for high performance, today's systems are running at faster and faster frequencies. This makes the AC performance of the interconnects on boards and backplanes more critical. Interconnect delay faults that used to be tolerable in slow systems may cause high performance systems to fail. To test for interconnect delay faults, today's common practice is to use bed-of-nails to measure the interconnect delays. Unfortunately, with the increasing usage of advanced silicon packaging technologies such as ball-grid-arrays (BGA), the applications of bed-of-nails have been significantly limited since many signals with the new packaging technologies are simply not observable on boards. In addition, the bed-of-nails approach does not cover delay faults in ASICs' (application specific integrated circuits') pad drivers and receivers damaged in the assembly process. Test vectors using bed-of-nails cannot be re-used at system levels or at customers' premises.
The causes of interconnect delay faults on boards and in systems are multiple. In the design phase, improper routings of some critical signals and/or improper terminations of these signals may contribute to excessive delays that will show up as interconnect delay faults after the board or system is assembled. Similarly, clock skews among different ASICs due to improper routings and/or unbalanced loads may even cause properly designed data signals to fail at speed. In the manufacturing phase, bad solder joints and defective tracks can cause interconnect delay faults. In addition, damaged ASIC pad drivers and receivers during board assembly and soldering process may also show up as interconnect delay faults.
In conventional manufacturing, AC performance test sometime falls between process flows. In in-circuit test station, DC characteristics (e.g. open, short, resistive and capacitive value, and analog devices) are the main targets of that stage of manufacturing. AC performance issues are usually covered in module test station or functional test station. Unless critical signals are identified and special tests are written to cover them, in general functional test on average does not have a high coverage on AC performance on most signals. With the new proposed technique, the ease of operation will make high coverage delay fault testing easily accommodated into either in-circuit test station or functional test station.
In a paper by P. K. Graham entitled “AC Interconnect Test with Series Boundary Scan”, IBM Tech. Disclosure Bulletin, Vol. 34, No. 6, November 1991, boundary scan driver cells and receiver cells were described to conduct AC interconnect test. Since it requires to enable the drivers under test all the time, it is unable to detect timing faults associated with the driver enable. U.S. Pat. No. 5,444,715 granted to Gruetzner et al. on Aug. 22, 1995 discloses that different boundary scan driver and receiver cells to overcome the deficiency in Graham's paper. It intends to test if data can be delivered from a driver cell to a receiver cell in one normal system clock cycle. The boundary scan cell described in both Graham's paper and U.S. Pat. No. 5,444,715 are not IEEE 1149.1 compatible.
A recently suggested technique uses a synchronizing trigger signal to conduct interconnect delay fault test of ASICs, implementing the IEEE 1149.1 standard. It helps reduce the dependency of interconnect delay tests on bed-of-nails. Under the control of a TAP controller, a special At-Speed Interconnect (ASI) controller is used to run the delay tests. This technique requires to add an extra pin to each ASIC that will be involved in board delay tests. The extra pins from ASICs are all connected together on board to provide a global synchronization signal that triggers the delay tests. This global signal can be driven by a tester or by a master ASI controller residing in one of the ASICs on the board. Due to board level functional signals connections, these extra pins cannot be easily shared with functional pins. In addition, it also requires to replace the standard boundary scan cells with their proprietary cells for all the pins involved in board delay tests. Each of these proprietary boundary scan cells contains an extra flip-flop running at system clock plus some specialized logics. This technique will only work for interconnects between two such equipped ASICs and not with any common off-the-shelf IEEE 1149.1 compliance components.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide an improved interconnect delay fault test.
According to one aspect of the present invention, there is provided a test access port (TAP) control method in use for fault test of interconnect between first and second integrated circuit (IC) chips, the method comprising the steps of: performing IEEE 1149.1 standard TAP operations wherein test clock (TCK), test mode select (TMS), TAP scan test clock (TAP—SCLK), TAP scan mode (TAP_SM) and TAP load (TAP_LO) signals are determined by standardized timing; generating a scan mode (SM) control signal in response to the TAP_SM signal; generating a load (LO) control signal in response to the TAP_LO signal; and generating a scan test clock (SCLK) control signal in response to the TCK signal and the LO control signal.
The TAP control method according to the present invention is based on the IEEE 1149.1 TAP operations to conduct fault test of interconnect between the IC chips. For example, IC chips are interconnected on a circuit board and they are ASICs (application specific integrated circuits) and commercially used chips such as CPUs (central processing units).
In the TAP control method, for example, the step of generating a scan mode (SM) control signal comprises the step of activating the SM control signal in response to the TAP_SM signal. The step of generating a load (LO) control signal comprises the step of activating the LO control signal in response to the TAP_LO signal. The step of generating a scan test clock (SCLK) control signal comprises the step of activating the SCLK control signal in response to the activated LO control signal. The LO control signal is activated in response to the succeeding edge of a pulse of the TAP_LO signal. The SCLK control signal is activated in response to the preceding edge of a pulse of the activated LO control signal with a time delay. The data stored in the boundary scan cells included in the first IC chip is transferred to the second IC chip via the interconnect between the first and second IC chips. The transferred data is captured by the second IC chip and stored in its boundary scan cells. This allows an interconnect delay fault test using the IEEE 1149.1 standard TAP operations.
According to another aspect of the present invention, there is provided an apparatus for conducting fault test of interconnect between first and second IC chips, the apparatus comprising a test access port (TAP) controller, the TAP controller performing IEEE 1149.1 standard TAP operations wherein test clock (TCK), test mode select (TMS), TAP scan test clock (TAPSCLK), TAP scan mode (TAP_SM) and TAP load (TAP_LO) signals are determined by standardized timing; the TAP controller generating means for generating scan mode (SM), load (LO) and scan test clock (SCLK) control signals, in response to the TAP_SM, the TAP_LO and the TCK signals.
In the apparatus, for example, each of the first and second IC chips comprises the TAP controller and boundary scan cells, the TAP controller comprising: means for generating the SM control signal in response to the TAP_SM signal; load control means for generating the LO control signal in response to the TAP_LO signal; and scan test clock means for generating the SCLK control signal in response to the TCK signal and the LO control signal. The TAP controller of the first IC chip further includes means for transferring data stored in

Affiliated with

Also associated with

Rating

Delay fault testing with IEEE 1149.1 does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Delay fault testing with IEEE 1149.1, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Delay fault testing with IEEE 1149.1 will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2531861