Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2007-10-25
2009-10-13
Smith, Zandra (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S216000, C438S287000, C438S591000
Reexamination Certificate
active
07601578
ABSTRACT:
A method for improving high-κ gate dielectric film (104) properties. The high-κ film (104) is subjected to a two step anneal sequence. The first anneal is performed in a reducing ambient (106) with low partial pressure of oxidizer to promote film relaxation and increase by-product diffusion and desorption. The second anneal is performed in an oxidizing ambient (108) with a low partial pressure of reducer to remove defects and impurities.
REFERENCES:
patent: 5786277 (1998-07-01), Yamamoto
patent: 6013553 (2000-01-01), Wallace et al.
patent: 6060755 (2000-05-01), Ma et al.
patent: 6162744 (2000-12-01), Al-Shareef et al.
patent: 6204203 (2001-03-01), Narwankar et al.
patent: 6413386 (2002-07-01), Callegari et al.
patent: 6544906 (2003-04-01), Rotondaro et al.
patent: 6689675 (2004-02-01), Parker et al.
patent: 7135361 (2006-11-01), Visokay et al.
patent: 7351626 (2008-04-01), Colombo et al.
Chambers James J.
Colombo Luigi
Pacheco Rotondaro Antonio Luis
Visokay Mark R.
Brady III Wade J.
Duong Khanh B
Garner Jacqueline J.
Smith Zandra
Telecky , Jr. Frederick J.
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