Deep trench body SOI contacts with epitaxial layer formation

Details Deep trench body SOI contacts with epitaxial layer formation Deep trench body SOI contacts with epitaxial layer formation

2001-08-06

2003-12-30

Lee, Eddie (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S348000, C257S349000, C438S149000, C438S479000, C438S517000

Reexamination Certificate

active

06670675

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a semiconductor device having a silicon-on-insulator (SOI) substrate and, more particularly, to formation of a deep trench contact in the SOI substrate.
2. Background Description
Integrated circuit technology relies on transistors to formulate vast arrays of functional circuits. The complexity of these circuits requires the use of an ever increasing number of linked transistors. As the number of transistors required increases, the surface area that can be dedicated to a single transistor declines. It is desirable then, to construct transistors which occupy less surface area on the silicon chip/die.
In one example, integrated circuit technology uses transistors conjunctively with Boolean algebra to create a myriad of digital circuits, also referred to as logic circuits. In a typical arrangement, transistors are combined to switch or alternate an output voltage between just two significant voltage levels, labeled logic 0 and logic 1. In an alternate example, integrated circuit technology similarly uses transistors combined with capacitors to form memory cells. Here, the data is stored in electronic form as a charge on the capacitor. The charge, or absence of charge, on the capacitor translates to either a logic 1 or 0. Most logic systems use positive logic, in which logic 0 is represented by zero volts, or a low voltage, e.g., below 0.5 V; and logic 1 is represented by a higher voltage.
Integrated circuits, including transistors, are typically formed from either bulk silicon starting material, silicon on insulator (SOI) starting material, or SOI material that is formed from a bulk semiconductor starting material during processing. The SOI complementary metal oxide semiconductor (CMOS) technology, however, has been viewed as a likely successor to conventional bulk technology since it provides a prospect of greater circuit performance. This increase in performance results from the lower parasitic junction capacitances and the improved transistor characteristics and tolerances. Basic to the feature of isolating the active silicon layer from the substrate by an intervening insulator layer is the so called “floating body” effect on device characteristics. Since the bodies of individual devices are not in direct electrical contact to the conducting substrate, their electrical potential can vary with time depending on leakage currents and parasitic capacitive coupling to other electrodes. Such an effect is clearly undesirable for products based on SOI technologies.
One approach to handle the uncertain body potential is to include margins within the circuit design to allow for the floating body effect. While this requires no technology action, it diminishes the performance benefits of SOI. Another approach is to minimize the floating body effect by providing an enhanced leakage path to the device body from the device source. This is a partial solution since it merely limits the amount by which the body potential may vary relative to the source and does not allow the voltage to be set at any particular optimum value. Further, it necessarily creates an electrically asymmetric device which limits its acceptability.
Other techniques include providing a separate conducting contact to the device bodies. For example,
FIG. 1
shows an SOI substrate divided into a peripheral region A and a device region B. A transistor is formed on the SOI substrate within the device region B. A gate electrode
22
is formed on the top substrate layer
14
with a gate oxide
20
therebetween, and source/drain regions
24
are formed in the top substrate layer
14
with a channel region therebetween. In the peripheral area A, a body contact
16
is formed between a top substrate layer
14
and a body substrate
10
via a buried contact
12
. However, this approach has proven cumbersome and comes at the price of increased chip sizes since an extra space for the body contact
16
and additional circuitry is required next to the device region B.
Thus what is needed is an improved method and structure for implementing SOI transistors, or devices, which provide a predictable electrical potential in the body of the device without sacrificing the benefits attained from using the SOI structure. An improved method and structure should also conserve surface space on the semiconductor die and maximize device density.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide an SOI device which conserves space on the semiconductor die without sacrificing the benefit attained from using the SOI structure.
Another object of the present invention is to provide a simplified but yet effective SOI body contact structure which does not require additional circuitry.
Still another object of the present invention is to provide a simplified and effective manufacturing method for an SOI device having a body contact.
Additional advantages and other features of the present invention will be set forth in part in the description which follows and will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a semiconductor device comprising an SOI substrate having top and bottom semiconductor layers separated by an insulator therebetween. Local insulation regions are formed in the top semiconductor layer of said SOI substrate. The local insulation regions define a device region. A contact is formed within said device region and extends between said top and bottom silicon layers and electrically connects said top and bottom semiconductor layers.
Another aspect of the present invention is a method for manufacturing a semiconductor device on an SOI substrate. The SOI substrate comprises top and bottom semiconductor layers and a buried insulation layer therebetween. The method comprises a step of defining a device region and a peripheral region in said SOI substrate. A contact is formed which extends from the top to bottom semiconductor layers via the buried insulation layer and electrically connects the top and bottom semiconductor layers. The contact is formed within the device region. An electric device is formed on the SOI substrate within the device region.
Thus, according to the present invention, a body contact is formed within the device region of an SOI substrate and an electric device, e.g., transistor is formed within the device region. This ensures a predictable electrical characteristics of the SOI device and conserves surface space on the die while still attaining the benefits from using the SOI structure.
Additional advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiment of the present invention is shown and described, simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be realized, the present invention is capable of other and different embodiments and its several details are capable of modifications in various obvious respects, all without departing from the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not restrictive.


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Robert Hannon et al., “0.25 &mgr;m Merged Bulk DRAM and SOI Logic using Patterned SOI,”IEEE 2000 Symposium on VLSI Technology Digest o

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