Deep mesa isolation

Details Deep mesa isolation Deep mesa isolation

1996-08-12

2000-09-19

Saadat, Mahshid

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257350, 257354, 257349, H01L 2701, H01L 2712, H01L 310392

Patent

active

061216585

ABSTRACT:
A method of making an integrated circuit in semiconductor on insulator material and the circuit which comprises providing a semiconductor on insulator structure having a device layer, preferably silicon, and an electrically insulating layer, the device layer being in contact with one surface of the electrically insulating layer. An underlayer is provided which contacts the opposing surface of the electrically insulating layer. The structure is then patterned and trenches are etched to expose a surface of the underlying layer and to form mesas extending from the underlying layer. Ions can now optionally be implanted into selected regions of the underlying layer. A dielectric is provided between the mesas extending to or into the substrate and fabrication of the integrated circuit is then completed. The dielectric can be a thermal oxide at the exposed surface with a dielectric over the thermal oxide. Prior to formation of the thermal oxide, a sidewall dielectric can be formed over the electrically conductive layer. The exposed surface of the dielectric between the mesas is preferably substantially coplanar with the top surface of the mesas.

REFERENCES:
patent: 4800527 (1989-01-01), Ozaki et al.
patent: 4914628 (1990-04-01), Nishimura
patent: 5241211 (1993-08-01), Tashiro
patent: 5581101 (1996-12-01), Ning et al.

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