Data transmission circuitry of a synchronous semiconductor memor

Details Data transmission circuitry of a synchronous semiconductor memor Data transmission circuitry of a synchronous semiconductor memor

1999-08-09

2000-10-03

Mai, Son

Static information storage and retrieval

Read/write circuit

Multiplexing

36518912, 3652385, 365233, G11C 700

Patent

active

061282332

ABSTRACT:
A synchronous memory comprising: a memory cell array being comprised of a plurality of memory cells; a clock control circuit for receiving a first clock signal, a second clock signal, and a third clock signal, and for generating an internal clock signal, a plurality of control signals, and a plurality of flag signals; a first register circuit for storing a plurality of input data bits in response to the internal clock signal and the control signals; a second register circuit for storing the flag signals in response to the internal clock signal and the control signals; a write drive circuit for writing the input data bits passing through the first register circuit into the memory cell array in response to the flag signals during a write cycle; a sense amplifier circuit coupled to the memory cell array; an address comparator circuit for receiving read and write address signals and for generating a first, a second, and a third combination signals; and a switching circuit for transferring the input data bits passing through the first register circuit and the flag signals passing through the second register circuit to output terminals of the device.

REFERENCES:
patent: 4891795 (1990-01-01), Pinkham et al.
patent: 5875132 (1999-02-01), Ozaki
patent: 5978307 (1999-11-01), Proebsting et al.
patent: 5978309 (1999-11-01), Seyyedy et al.

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