Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Metastable state prevention
Patent
1995-10-06
1996-11-19
Westin, Edward P.
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
Metastable state prevention
327218, 327 98, H03K 1900
Patent
active
055766439
ABSTRACT:
A data transfer circuit device including a data transfer circuit, a latch control circuit and a data latch circuit. The data transfer circuit outputs data therefrom in response to an externally supplied transfer signal. The latch control circuit generates a data latch signal, based on the transfer signal and a latch control signal. The data latch circuit latches the data supplied from the data transfer circuit, based on the data latch signal, and outputs the latched data as output data. When the data is being switched, the latch control circuit prevents the data latch signal from being supplied to the data latch circuit.
REFERENCES:
patent: 5036221 (1991-07-01), Brucceleri
patent: 5122694 (1992-06-01), Bradford
patent: 5233617 (1993-08-01), Simmons
patent: 5239206 (1993-08-01), Yanai
patent: 5410550 (1995-04-01), Simmons
Kobayashi Isamu
Yamamoto Yasuhiro
Fujitsu Limited
Sanders Andrew
Westin Edward P.
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